Semiconductor device and manufacturing metthod thereof

ABSTRACT

A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

This application is the first of two concurrently filed DivisionalApplications of U.S. application Ser. No. 10/374,997, filed Feb. 28,2003, which, in turn, is a CIP (Continuation-In-Part) of (i) U.S.application Ser. No. 09/768,288, filed Jan. 25, 2001, and now abandoned,of (ii) U.S. application Ser. No. 09/771,985, filed Jan. 30, 2001, andnow abandoned, and of (iii) U.S. application Ser. No. 09/983,286, filedOct. 23, 2001, and now U.S. Pat. No. 6,639,323, said U.S. applicationSer. Nos. 09/768,288 and 09/771,985 are, in turn, a continuationapplication and a divisional application, respectively, of U.S.application Ser. No. 09/449,834, filed Nov. 26, 1999, and now U.S. Pat.No. 6,342,726, which, in turn, was filed as a continuation of U.S.application Ser. No. 08/822,933, filed Mar. 21, 1997, and now abandoned,and said U.S. application Ser. No. 09/983,286, is a continuation of U.S.application Ser. No. 09/113,500, filed Jul. 10, 1998, and now U.S. Pat.No. 6,307,269; and the entire disclosures of all of which are herebyincorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates, generally, to a semiconductor devicetechnique such as for the manufacture of a semiconductor integratedcircuit device and, in particular, relates to a technique useful in themanufacture of a semiconductor device such as a semiconductor integratedcircuit device to be applied to portable equipment, such as portabletelephones and handy type personal computers, for which there is astrong trend toward reducing the size, the weight and the thickness ofthe product and, also, to such technique which leads to the manufactureof a relatively low cost semiconductor device such as a low costsemiconductor integrated circuit device package with improved sealproperties in the package such as a CSP (Chip Size Package), althoughnot limited thereto.

1. Recently, a trend toward reducing the size, the weight and thethickness of the product has become vigorous for electronic equipmentalong with an improved function and performance. This is largely due toa rapid increase in the use of personal equipment, such as personaltelephones or handy type personal computers in recent years. Further,man-machine interface functions have been increased in personallymanipulated equipment, for which easy handlability and operability havebeen considered increasingly important. It is considered that the trendwill become more and more conspicuous in expected regular multimediaareas.

Under such circumstances, development for increasing the density and thedegree of integration of semiconductor chips has progressedcontinuously; however, in addition to the size and the number ofelectrodes of the semiconductor chips being increased, the size of thepackages have also increased rapidly. Accordingly, narrowing of thepitch of terminal leads has been promoted for facilitating the sizereduction of the packages, which makes mounting of the package moredifficult.

In view of the above, it has been proposed in recent years to providehigh density packages with super-multiple pins having the same area asthat of the semiconductor chips, and such packaging techniques arementioned, for example, in various publications, such as “NikkeiMicrodevices” p 98-p 102, issued on May 1, 1994, “Nikkei Microdevices” p96-p 97, issued on Feb. 1, 1995 by Nikkei BP Co. and “ElectronicMaterial”, p 22-p 28, issued on Apr. 1, 1995 (Heisei 7) by KogyoChosakai. One example of the structures produced with such packagingtechniques, for example, as described in FIG. 6 of the “ElectronicMaterial” publication, has a package structure in which a flexiblewiring substrate is disposed by way of an elastomer (elastic material)on the surface of a semiconductor chip, leads on one end of wirings ofthe flexible wiring substrate are electrically connected with bondingpads on the surface of the semiconductor chip, and bump lands on theother end of the wirings of the flexible wiring substrate areelectrically connected with the solder bumps.

The package structure has an outer size about equal to or greater thanthat of a semiconductor chip by the size of a protection frameoptionally attached to the periphery of the chip, for which a flexiblewiring substrate formed with solder bumps is used. The wiring pattern ofthe wiring substrate is made of a Cu foil having a Au plating on oneside, the top ends of which to be connected with the pad of the chipconstitute a lead pattern which is only composed of Au as a result ofetching the Cu foil. In this structure, the flexible wiring substrate isbonded by an elastomer on the surface of the semiconductor chip and thenthe Au leads are connected with the bonding pads of the semiconductorchip.

2. A CSP, for example, which is a thin, compact semiconductor device ofchip size, is often used in printed circuit boards built into portableelectronic devices such as that referred-to above. The general structureof a CSP comprises a thin film wiring substrate on which are mountedbump electrodes which are external terminals, leads electricallyconnected to electrode pads of a semiconductor chip, an elastomer(elastic structure/elastic structural material) arranged between thesemiconductor chip and the thin film wiring substrate and havingapproximately the same size as the thin film wiring substrate, andsealing parts which seal the electrode pads and the leads of the thinfilm wiring substrate connected to it.

Structures of CSPs studied by the inventors for comparison purposes,also, are described, for example, in “Nikkei Microdevices” Apr. 1, 1997,No. 142, pp. 44-53, published by Nikkei BP Co. on Apr. 1, 1997, and, inparticular, the next generation CSP structure (comparison examples)described in FIG. 6, on page 48 thereof. This CSP comprises asemiconductor chip having electrode pads formed on its main surface,bump electrodes which are external terminals over the main surface ofthe semiconductor chip, and a contour ring outside the semiconductorchip.

SUMMARY OF THE INVENTION

In a study made by the present inventors of the package structure asdescribed in part 1 above, a number of problems were recognized. Forexample, since the flexible wiring substrate in the package structuredescribed above has a structure typically represented by a TCP (TapeCarrier Package) in which a Cu wiring pattern is formed on the surfaceof a polyimide tape, and an elastomer is formed to the wiring substrateon the side of the wiring surface, it is difficult to mount theelastomer uniformly and stably because of unevenness of the wiringpattern on the flexible wiring substrate. That is, there exist suchproblems that voids not filled with the elastomer are formed near bothsides of the protrusions of the wiring pattern upon coating or appendingthe elastomer on the flexible wiring substrate, and the step of bondingthe semiconductor chip can not be conducted stably since the size andthe shape of the elastomer are not stable.

Further, bump electrodes are formed on the wiring substrate on the sideof the tape. That is, a bump electrode is connected with the wirings byway of a through hole formed in the tape. Since the thickness of thetape is relatively large, for example, as much as 50 μm, if the pitchbetween the bump electrodes is smaller than the thickness of the tape,the aspect ratio of the through hole is increased to bring about aconcern that the bump electrode and the wiring will not be connected.Accordingly, there is a concern that an increase in the number of pinsof the package may be restricted.

In view of the above, an object of the present invention is to provide asemiconductor integrated circuit device capable of mounting an elasticstructural material to a wiring substrate stably with a high accuracyand making the bonding step of a semiconductor chip stable, therebyenabling assembling with a high yield.

Another object of the present invention is to provide a technique forpromoting an increase in the number of pins in a package.

An object of the present invention is to provide a semiconductorintegrated circuit device capable of obtaining excellent electricalproperties in view of noise resistance by the adoption of a multiplewiring layer structure.

An object of the present invention is to prevent wiring from becomingcontaminated ingredients of an elastic structural material.

An object of the present invention is to prevent a semiconductor chipfrom being damaged, improve the reliability of the semiconductor chip,as well as prevent connection failure between an elastic structuralmaterial and the semiconductor chip, worsening of the flatness of thewiring substrate and lowering of reliability.

An object of the present invention is to eliminate a requirement for asoft-modified special wire bonder and to effect a shortening of thecontact time upon bonding by further simplifying the trace of thebonding tool.

An object of the present invention is to solve a problem concerningdisconnection of wirings.

An object of the present invention is to reduce any damage to apassivation layer or a semiconductor chip therebelow and further improvethe bondability by preventing contamination of the wirings.

An object of the present invention is to increase the bonding strengthbetween wirings and a substrate material and obtain a stable notchcutting performance.

An object of the present invention is to suppress warp of a wiringsubstrate and improve bondability with a bonding material, so as toachieve a package having excellent moisture proofness and reliability.

An object of the present invention is to improve the groove-fillagecapability of an elastic structural material, capable of increasing thestrength of a metal mask, by using a plurality of one side bridgingportions, and further improving the groove-fillage capability by theformation of a stopping dam for sealant flow.

An object of the present invention is to improve the bondability andprevent damage to a semiconductor chip in an inner lead bondingtechnique.

An object of the present invention is to form a suitable S-shapedconfiguration with no return of a bonding tool but by merely driving thebonding tool vertically using a wiring design which takes intoconsideration a bending stress ratio.

An object of the present invention is to reduce the occurrence of cracksin wirings per se and moderate bonding damage to a semiconductor chip.

An object of the present invention is to suppress bleeding of lowmolecular weight ingredients of an elastic structural material andfurther avoid a disadvantage involving the creation of voids uponforming the elastic structural material by surface flattening.

An object of the present invention is to improve the fabricationaccuracy for hole diameter for connection of a bump electrode in amethod of manufacturing a semiconductor integrated circuit.

An object of the present invention is to provide a technique for forminga semiconductor package which is capable of bonding bump electrodes moresatisfactorily, reducing the pitch of the bump electrodes and whichprovides output terminals at a higher density in a method ofmanufacturing a semiconductor integrated circuit device.

These and other objects, as well as novel features of the presentinvention will become apparent by consideration of the descriptions inthe specification with reference to the accompanying drawings.

Among the featured aspects disclosed in the present application, asummary of typical examples thereof is given below.

That is, one of the semiconductor integrated circuit devices accordingto the present invention provides a package structure applied to asemiconductor integrated circuit device in which a wiring substrate isdisposed by way of an elastic structural material on a main surface of asemiconductor chip, lead portions on one end of the wirings of thewiring substrate are electrically connected with external terminals onthe main surface of the semiconductor chip, and land portions on theother end of the wirings of the wiring substrate are electricallyconnected with bump electrodes, wherein the wiring substrate has wiringsformed on a first, main surface of a substrate base material (tape), andan elastic structural material is disposed on a second surface of thesubstrate base material, opposite the main surface thereof.

Further, the bump electrodes are formed on the side of the wirings.

Further, the bump electrodes are connected with the wirings each by wayof a through hole disposed in an insulation film formed on the wiringsand having a thickness smaller than that of the wiring base material.

Further, the external terminals of the semiconductor chip are disposedat a central portion or at an outer circumferential portion (i.e., at anouter periphery) of the semiconductor chip, and the bump electrodesconnected to the external terminals of the semiconductor chip by way ofthe wirings of the wiring substrate are disposed to the inside, outsideor in both regions inside and outside with respect to the outercircumference of the semiconductor chip.

Further, in a semiconductor integrated circuit device of the presentinvention, the size of the end of the elastic structural member of thesemiconductor chip on the side of the external terminals and the end ofthe substrate base material of the wiring substrate are determined basedon the ingredients of the elastic structural material.

Further, in a semiconductor integrated circuit device of the presentinvention, a distance M2 between the end of the substrate base materialof the wiring substrate and the end of the elastic structural materialon the outer circumferential side of the semiconductor integratedcircuit device, and a distance M1 between the end of the semiconductorchip and the end of the substrate base material are determined within arange capable of satisfying the relationship:M1>M2>0.

Further, in a semiconductor integrated circuit device of the presentinvention, the wirings of the wiring substrate are formed to such ashape that a portion fixed with the substrate base material of thewiring substrate and a top end portion connected to the externalterminals of the semiconductor chip are displaced at least by more thanthe width of the wirings.

Further, in a semiconductor integrated circuit device of the presentinvention, the wirings of the wiring substrate are formed as acantilever structure fixed at one side to the substrate base material ofthe wiring substrate.

Further, in a semiconductor integrated circuit device of the presentinvention, the size of the end of an opening in a surface protectionfilm on the semiconductor chip is determined within such a range thatthe wirings do not interfere with the surface protection film at leaston the side thereof on which a bonding tool is driven down.

Further, in a semiconductor integrated circuit device of the presentinvention, the wirings of the wiring substrate are formed such that aneffective area of a wiring portion of the wiring on the side of thenotch terminal end is made larger. Particularly, the wiring portion onthe side of the notch terminal end is connected with an opposed landportion of the wirings, or is extended longitudinally or laterally in avacant region of the wirings, or adjacent wirings are connected witheach other.

Further, in a semiconductor integrated circuit device of the presentinvention, the elastic structural material is formed within a rangegreater over the entire circumference at least by more than the width ofa protrusion at the outer circumferential portion formed in the elasticstructural material.

Further, in a semiconductor integrated circuit device of the presentinvention, when the elastic structural material is formed in two partsso as not to be bonded on the external terminals of the semiconductorchip, each of the ends of spaces to which the divided elastic structuralmaterials are opposed is formed in a groove-shape. Particularly, aplurality of grooves are formed at each of the ends of the elasticstructural material, or a stepping dam for sealant flow is formedbeforehand during a sealing step.

Further, in a semiconductor integrated circuit device of the presentinvention, the connection structure between the external terminals ofthe semiconductor chip and the wirings of the wiring substrate areformed by pre-forming stud bumps on the external terminals of thesemiconductor chip, and the external terminals of the semiconductor chipand the wirings of the wiring substrate are connected by way of the studbumps.

Further, in a semiconductor integrated circuit device of the presentinvention, the connection structure between the external terminals ofthe semiconductor chip and the wiring substrate is formed by supplyingsolder beforehand so as to surround the wirings of the wiring substrateand the external terminals of the semiconductor chip, and the externalterminals of the semiconductor chip are connected by way of the solder.

Further, in a semiconductor integrated circuit device of the presentinvention, the connection structure between the external terminals ofthe semiconductor chip and the wirings of the semiconductor substrateare formed by connecting the wirings of the wiring substrate and theexternal terminals of the semiconductor chip by way of stud bumps byusing stud bumps of solder or Au ball so as to surround the wirings ofthe wiring substrate from above.

Further, in a semiconductor integrated circuit device of the presentinvention, the connection structure between the external terminals ofthe semiconductor chip and the wirings of the wiring substrate areformed by connecting the wirings of the wiring substrate and theexternal terminals of the semiconductor chip by using Al, solder or Auwire.

Further, in a semiconductor integrated circuit device of the presentinvention, the wiring structure of the wiring substrate is formed bynarrowing the lateral size of the wirings from the end of the substratebase material of the wiring substrate to the top end of the wirings,such that the bending stress ratio α is represented by:α=σ1/σ0where σ0 is bending strength caused at the end of the substrate basematerial and σ1 is maximum stress caused at an intermediate portionbetween the end of the substrate base material and the top end of thewirings, and wherein the lateral size is made constant particularly froma predetermined position, and the size and the shape of the wirings aredetermined such that the bending stress ratio α is from 1.2 to 1.5 in acase where the bending stress ratio α is represented by the followingformula:α=b 1×(L 2−L 1)/b 2×L 2)in which L1 is a taper length, L2 is a wiring length, b1 is a taperwidth and b2 is a wiring width.

Further, in a semiconductor integrated circuit device of the presentinvention, the wiring structure of the wiring substrate is formed byusing an electroconductive material as a core material and applying Auplating on the surface.

Further, the wiring structure of the wiring substrate is formed by usingCu as a core material, applying Au plating on the surface and making atleast one end connected with the external electrodes of the chip into anS-shaped configuration.

Further, in a semiconductor integrated circuit device of the presentinvention, a flattening insulation film is formed on the wiringsubstrate on the side of the wirings and an elastic structural materialis disposed on the insulation film.

Further, a method of manufacturing a semiconductor integrated circuitdevice according to the present invention comprises a step of forming anelastic structural material on the rear face of a wiring substrate (tapeside) in which wirings are formed on the substrate base material (tape),a step of bonding a semiconductor chip to the surface of the elasticstructural material so as to oppose the wiring substrate, a step ofconnecting one end of the wirings to the external terminals of thesemiconductor chip, a step of forming an insulation film thinner thanthe substrate base material on a main surface of the wirings, a step offorming openings to the insulation film each at a position correspondingto the other end of the wirings to be joined with the bump electrodes,and a step of forming the bump electrodes being joined to the other endof the wirings by way of the wirings.

Additionally, in a semiconductor device package structure like the CSPhaving the aforesaid general structure, discussed in part 2 above,problems due to resin flow of the package sealant arise. For example, asealing resin easily flows onto the sides of the semiconductor chip.This impairs the precision of the contour size of the CSP so that, insome cases, it could not be inserted in its socket. In other words, aproblem arises in that the contour shape of the CSP does not remainfixed.

If the amount of sealing resin is reduced in an attempt to solve such aproblem in the case of the aforementioned CSP, the leads of the thinfilm wiring substrate may be exposed. This would adversely affect thesealing properties of the package. Namely, the sealing properties of thesealing parts would become inadequate, and humidity resistance would nolonger be reliable.

In the comparison of CSP structures of the prior art, if the contourring is made a separate structure, manufacturing costs increase.

In a CSP having the usual structure, during solder reflow in forming thebump electrodes, the internal pressure rises due to expansion ofmoisture and gas in the elastomer, and, as a result, the seal part isdestroyed causing a “popcorn” phenomenon.

It is, therefore, also an object of this invention to provide a chipsize semiconductor device of lower cost and improved sealing properties,and a method of manufacturing such a device.

It is a further object of this invention to provide a semiconductordevice and manufacturing method which prevents occurrence of theaforementioned popcorn phenomenon.

These additional and other features of the invention are summarizedbelow with regard to the description of further examples of the featuredinventive aspects of the present application.

In a semiconductor device of this invention, a chip size package has itsconnection terminals provided on the outer periphery of its mainsurface. Such a package comprises an elastic structure arranged on themain surface of the semiconductor chip leaving the connection terminalsexposed, a thin film wiring substrate comprising a substrate body havingwirings whereof first ends thereof are electrically connected to theaforesaid terminals via leads and the other ends thereof areelectrically connected to bump electrodes which are external terminalsand comprising substrate protruding parts having openings which leavethe connection terminals exposed and which protrude beyond the openingsand the semiconductor chip, and sealing parts which seal the connectionterminals of the semiconductor chip and seal the leads of the thin filmwiring substrate, the substrate body and the substrate protruding partsof the thin film wiring substrate being formed in a one-piececonstruction.

As the substrate protruding parts are not separate from the substratebody but are formed together with it in a one-piece construction, thesubstrate protruding parts need not be formed from costly materials. Asa result, the cost of manufacturing the semiconductor device is reduced.

Further, in a semiconductor device of this invention, a chip sizestructure has its connection terminals provided on the outer peripheryof its main surface. Such a device comprises an elastic structurearranged on the main surface of the semiconductor chip comprisingelastic protruding parts having openings which leave the connectionterminals exposed, a thin film wiring substrate comprising a substratebody having wirings whereof first ends thereof are electricallyconnected to the aforesaid terminals via leads and the other endsthereof are electrically connected to bump electrodes which are externalterminals, and comprising substrate protruding parts having openingswhich leave the connection-terminals exposed and which protrude beyondthe openings and the semiconductor chip, and sealing parts which sealthe connection terminals of the semiconductor chip and seal the leads ofthe thin film wiring substrate, the substrate body and the substrateprotruding parts of the thin film wiring substrate being formed in aone-piece construction, and the thin film wiring substrate and theelastic structure having substantially the same size.

Still further, in a semiconductor device of this invention, a chip sizestructure has its connection terminals provided on the outer peripheryof its main surface, comprising an elastic structure arranged on themain surface of the semiconductor chip having parts exposed to theoutside for exposing the connection terminals, a thin film wiringsubstrate comprising a substrate main body having wirings whereof firstends thereof are electrically connected to the aforesaid connectionterminals via leads and the other ends thereof are electricallyconnected to bump electrodes which are external terminals, andcomprising openings so as to expose the aforesaid connection terminals,and sealing parts which seal the connection terminals of thesemiconductor chip and seal the leads of the thin film wiring substrate.

A method of manufacturing a semiconductor device according to thisinvention comprises a step for preparing a thin film wiring substratewhich is a chip size structure having connection terminals provided onthe outer periphery of its main surface, comprising a substrate bodywith wiring, and comprising substrate protruding parts which protrudebeyond openings in which leads are connected to this wiring and formedin a one-piece construction with the substrate body, a step for joiningan elastic structure and the substrate body of the thin film wiringsubstrate, a step for joining the main surface of the semiconductor chipand the elastic structure so as to expose the connection terminals ofthe semiconductor chip in the openings of the thin film wiringsubstrate, a step for electrically connecting the connection terminalsof the semiconductor chip and the corresponding leads of the thin filmwiring substrate, a step for sealing the connection terminals of thesemiconductor chip and the leads of the thin film wiring substrate usinga sealing resin comprising a low silica material so as to form sealingparts, a step for electrically connecting the wiring of the substratebody so as to form bump electrodes, and a step for simultaneouslycutting the substrate protruding parts and sealing parts formed thereinto a desired contour size.

Further, a method of manufacturing a semiconductor device according tothis invention comprises a step for preparing a thin film wiringsubstrate which is a chip size structure having connection terminalsprovided on the outer periphery of its main surface, comprising asubstrate main body having wiring joined to an elastic structure andopenings in which leads are connected to the wiring, wherein thesubstrate body is supported in a substrate frame by supporting parts ofthe elastic structure, a step for joining the main surface of thesemiconductor chip and the elastic structure so as to leave theconnection terminals of the semiconductor chip exposed in the openingsof the thin film wiring substrate, a step for electrically connectingthe connection terminals of the semiconductor chip and the correspondingleads of the thin film wiring substrate, a step for resin sealing theconnection terminals of the semiconductor chip and the leads of the thinfilm wiring substrate so as to form sealing parts, a step forelectrically connecting the wiring of the substrate body so as to formbump electrodes, a step for cutting the supporting part of the elasticstructure so as to separate the substrate body from the substrate frame,and a step for exposing the exposed parts of the elastic structure.

The foregoing and a better understanding of the present invention willbecome apparent from the following detailed description of theillustrated embodiments and the claims when read in conjunction with theaccompanying drawings, all forming a part of the invention. While theforegoing and following written and illustrated disclosure focuses ondisclosing various example embodiments depicted as preferred embodimentsof the invention, it should be clearly understood that the same is byway of illustration and example only and is not to be construed as beinglimited thereto. The spirit and scope of the present invention arelimited only by the terms of the appended claims.

The following represents brief descriptions of the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a semiconductor integrated circuitdevice which represents an Embodiment 1 of the present invention;

FIG. 2 is a cross sectional view taken along line 2-2 in FIG. 1 of theEmbodiment 1 according to the present invention;

FIG. 3 is a plan view illustrating the state of mounting thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention to a mounting substrate;

FIG. 4 is a cross sectional view illustrating the state of mounting thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention to a mounting substrate;

FIG. 5 is a flow chart illustrating the steps of assembling thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 6 is a cross sectional view of a main portion of the semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 7 is a cross sectional view of a main portion for comparativeexplanation of the semiconductor integrated circuit device of theEmbodiment 1 according to the present invention and a semiconductorintegrated circuit device studied by the present inventors;

FIG. 8 is a cross sectional view of a main portion illustrating bothface wirings as a modified embodiment of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

FIG. 9 is a plan view illustrating a window opening portion of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 10 is a cross sectional view corresponding to the window opening inFIG. 9;

FIG. 11 is a cross sectional view for explaining the size of a windowopening and an edge portion of the semiconductor chip in a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 12 is a cross sectional view illustrating a concave shape of anelastomer after printing of a semiconductor integrated circuit device inthe Embodiment 1 according to the present invention;

FIG. 13 is a cross sectional view illustrating a tape warping afterappending a semiconductor chip in a semiconductor integrated circuitdevice of the Embodiment 1 according to the present invention;

FIG. 14 is a plan view illustrating a planar S-shaped lead of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 15 is a cross sectional view as seen in the direction of arrow B inFIG. 14 of a semiconductor integrated circuit device in the Embodiment 1according to the present invention;

FIG. 16 is a cross sectional view as seen in the direction of arrow A inFIG. 14 in a semiconductor integrated circuit device in the Embodiment 1according to the present invention;

FIG. 17 is a cross sectional view illustrating a trace of a bonding toolupon forming a standard S-shaped lead in a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

FIG. 18 is a cross sectional view illustrating a trace of a bonding toolupon forming a planar S-shaped lead in a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

FIG. 19 is a plan view for explaining a notch lead and a beam lead of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 20 is a plan view illustrating a notch lead at the portion A inFIG. 19 of a semiconductor integrated circuit device in the Embodiment 1according to the present invention;

FIG. 21 is a plan view illustrating a beam lead of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 22 is a cross sectional view illustrating a lead bonding portion ofa semiconductor integrated circuit device in the Embodiment 1 accordingto the present invention;

FIG. 23 is a plan view illustrating a lead bonding portion of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 24 is a cross sectional view illustrating, in an enlarged scale, alanding position of a tool in the portion A in FIG. 22, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 25 is a cross sectional view illustrating a bonding portionimproved for the size of a passivation opening, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 26 is a plan view illustrating a bonding portion for leadsextending in both directions of a semiconductor integrated circuitdevice in the Embodiment 1 according to the present invention;

FIG. 27 is a plan view illustrating standard anchor wirings, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 28 is a plan view illustrating improved anchor wirings, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 29 is a perspective view illustrating a structure of a standardelastomer, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 30 is a perspective view illustrating a state of appending asemiconductor chip at a standard elastomer, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 31 is a perspective view illustrating a structure of a wideelastomer, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 32 is a perspective view illustrating a state of appending asemiconductor chip at a wide elastomer, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

FIG. 33 is a cross sectional view illustrating a state of appending asemiconductor chip at a wide elastomer, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

FIG. 34 is a perspective view illustrating a structure of the standardelastomer after appending a semiconductor chip, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 35 is a cross sectional view illustrating a structure of a standardelastomer after appending the semiconductor chip, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 36 is a perspective view illustrating a structure of a wideelastomer after appending the semiconductor chip, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 37 is a cross sectional view illustrating a structure of a wideelastomer after appending the semiconductor chip, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 38 is a cross sectional view illustrating a concept of metal maskprinting, of a semiconductor integrated circuit device in the Embodiment1 according to the present invention;

FIG. 39 is a plan view illustrating a metal mask of a standardelastomer, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 40 is a plan view illustrating a metal mask of a wide elastomer, ofa semiconductor integrated circuit device in the Embodiment 1 accordingto the present invention;

FIG. 41 is a plan view illustrating a printed shape for a plurality ofsuspended wide elastomers, of a semiconductor integrated circuit devicein the Embodiment 1 according to the present invention;

FIG. 42 is a plan view illustrating a potting position forgroove-fillage of a wide elastomer, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

FIG. 43 is a cross sectional view illustrating a bonding portion by astandard lead bonding, of a semiconductor integrated circuit device inthe Embodiment 1 according to the present invention;

FIG. 44 is a cross sectional view illustrating a bonding portion byusing stud bumps, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 45 is a cross sectional view illustrating a lead connection byusing solder, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 46 is a plan view illustrating a lead connection using solder, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 47 is a cross sectional view illustrating a lead connection byusing solder or Au ball, of a semiconductor

-   -   integrated circuit device in the Embodiment 1 according to the        present invention;

FIG. 48 is a perspective view illustrating a lead connection by usingsolder or Au ball, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 49 is a cross sectional view illustrating a lead connection byusing Al or soldering wire, of a semiconductor integrated circuit devicein the Embodiment 1 according to the present invention;

FIG. 50 is a cross sectional view illustrating a lead connection byusing an Au wire, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 51 is a perspective view for explaining a lead design, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

FIG. 52 is a perspective view illustrating modification of a lead afterbonding, of a semiconductor integrated circuit device in the Embodiment1 according to the present invention;

FIG. 53 is chart illustrating a relationship between a lead size and abending stress ratio, of a semiconductor integrated circuit device inthe Embodiment 1 according to the present invention;

FIG. 54 is a cross sectional view illustrating a connection portion oflead connection, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 55 is an enlarged cross sectional view illustrating a lead bentportion, of a semiconductor integrated circuit device in the Embodiment1 according to the present invention;

FIG. 56 is an enlarged cross sectional view illustrating aNi-platingless lead bent portion, of a semiconductor integrated circuitdevice in the Embodiment 1 according to the present invention;

FIG. 57 is an enlarged cross sectional view illustrating a lead presscontact portion, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 58 is an enlarged cross sectional view illustrating aNi-platingless lead press contact portion, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

FIG. 59 is a cross sectional view illustrating a structure of asemiconductor integrated circuit device in an Embodiment 2 according tothe present invention;

FIG. 60 is a perspective view illustrating a structure of asemiconductor integrated circuit device in the Embodiment 2 according tothe present invention;

FIG. 61 is a plan view, as viewed from the rear face of a semiconductorchip, of a semiconductor integrated circuit device in the Embodiment 3according to the present invention;

FIG. 62 is a plan view illustrating a semiconductor integrated circuitdevice in the Embodiment 3 according to the present invention;

FIG. 63 is a cross sectional view illustrating a semiconductorintegrated circuit device in the Embodiment 3 according to the presentinvention;

FIG. 64 is an enlarged cross sectional view illustrating a portion A inFIG. 63, of a semiconductor integrated circuit device in the Embodiment3 according to the present invention;

FIG. 65 is a plan view for explaining a wiring structure of a wiringsubstrate, of a semiconductor integrated circuit device in theEmbodiment 3 according to the present invention;

FIG. 66 is a plan view, as viewed from the rear face of a semiconductorchip, of a semiconductor integrated circuit device as an Embodiment 4according to the present invention;

FIG. 67 is a plan view illustrating a semiconductor integrated circuitdevice in the Embodiment 4 according to the present invention;

FIG. 68 is a cross sectional view illustrating a semiconductorintegrated circuit device in the Embodiment 4 according to the presentinvention;

FIG. 69 is an enlarged cross sectional view illustrating a portion A inFIG. 68, of a semiconductor integrated circuit device in the Embodiment4 according to the present invention;

FIG. 70 is a plan view for explaining a wiring structure of a wiringsubstrate, of a semiconductor integrated circuit device in theEmbodiment 4 according to the present invention;

FIG. 71 is a plan view, as viewed from the rear face of a semiconductorchip, of a semiconductor integrated circuit device in the Embodiment 5according to the present invention;

FIG. 72 is a plan view illustrating a semiconductor integrated circuitdevice in the Embodiment 5 according to the present invention;

FIG. 73 is a cross sectional view illustrating a semiconductorintegrated circuit device in the Embodiment 5 according to the presentinvention;

FIG. 74 is an enlarged cross sectional view illustrating a portion A inFIG. 73, of a semiconductor integrated circuit device in the Embodiment5 according to the present invention;

FIG. 75 is a plan view for explaining a wiring structure of a wiringsubstrate, of a semiconductor integrated circuit device in theEmbodiment 5 according to the present invention;

FIG. 76 is a cross sectional view illustrating the modified shape of thelead in accordance with the bending stress ratio in a comparativeexplanation between the semiconductor integrated circuit device in theEmbodiment 1 according to the present invention and the semiconductorcircuit device studied by the present inventors;

FIG. 77 is a cross sectional view illustrating the modified shape of thelead in accordance with the bending stress ratio, of the semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 78 is a cross sectional view illustrating the modified shape of thelead in accordance with the bending stress ratio, of the semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 79 is a cross sectional view illustrating the modified shape of thelead in accordance with the bending stress ratio, of the semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 80 is a cross sectional view illustrating the modified shape of thelead in accordance with the bending stress ratio, of the semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

FIG. 81 is a cross sectional view illustrating a modified example of apackage structure, of the semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

FIG. 82 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to an Embodiment 6 of thepresent invention;

FIGS. 83(a) to 83(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 82, in which FIG. 83(a) is across-sectional view through a line 83A-83A in FIG. 82, FIG. 83(b) is across-sectional view through a line 83B-83B in FIG. 82, and FIG. 83(c)is a cross-sectional view through a line 83C-83C in FIG. 82;

FIGS. 84(a), 84(b), 84(c) and 84(d) are specification tables showingexample specifications of parts used in the semiconductor device shownin FIG. 82;

FIG. 85 is a manufacturing sequence showing a typical process formanufacturing the semiconductor device shown in FIG. 82;

FIG. 86 is a chart showing typical processing conditions in each stageof the production process shown in FIG. 85;

FIGS. 87(a), 87(b) are partial plan views showing a typical method ofmanufacturing a thin film wiring substrate used for a semiconductordevice (CSP) according to Embodiment 6 of the present invention;

FIGS. 88(a), 88(b) are partial plan views showing a typical method ofmanufacturing a thin film wiring substrate used for a semiconductordevice (CSP) according to Embodiment 6 of the present invention;

FIGS. 89(a), 89(b) are partial plan views showing a typical method ofmanufacturing a thin film wiring substrate used for a semiconductordevice (CSP) according to Embodiment 6 of the present invention;

FIGS. 90(a) and 90(b) are diagrams each showing a typical method ofmanufacturing the semiconductor device (CSP) according to the firstembodiment of this invention, in which FIG. 90(a) is a partial plan viewshowing an elastomer attachment, and FIG. 90(b) is a partial plan viewshowing a semiconductor chip attachment;

FIG. 91 is a partial plan view showing an example of a cutting positionin a method of manufacturing a semiconductor device (CSP) according toEmbodiment 6 of the present invention;

FIGS. 92(a), 92(b) are perspective views showing an example of a leadcutting method in a method of manufacturing the semiconductor device(CSP) according to Embodiment 6 of the present invention;

FIGS. 93(a), 93(b), 93(c) are perspective views showing an example of anelastomer attachment state in a method of manufacturing a semiconductordevice (CSP) according to Embodiment 6 of the present invention;

FIGS. 94(a), 94(b) are perspective views showing an example of a leadbonding method in a method of manufacturing a semiconductor device (CSP)according to Embodiment 6 of the present invention;

FIG. 95 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 7 of the presentinvention through the sealing parts;

FIGS. 96(a) to 96(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 95, in which FIG. 96(a) is across-sectional view through a line 96A-96A in FIG. 95, FIG. 96 b) is across-sectional view through a line 96B-96B in FIG. 95, and FIG. 96(c)is a cross-sectional view through a line 96C-96C in FIG. 95;

FIG. 97 is a plan view showing an example of a structure of asemiconductor device (CSP) according to Embodiment 8 of the presentinvention through the sealing parts;

FIGS. 98(a) to 98(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 97, in which FIG. 98(a) is across-sectional view through a line 98A-98A in FIG. 97, FIG. 98(b) is across-sectional view through a line 98B-98B in FIG. 97, and FIG. 98(c)is a cross-sectional view through a line 98C-98C in FIG. 97;

FIG. 99 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 9 of the presentinvention through the sealing parts;

FIGS. 100(a) to 100(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 99, in which FIG. 100(a) is across-sectional view through a line 100A-100A in FIG. 99, FIG. 100(b) isa cross-sectional view through a line 10B-10B in FIG. 99, and FIG.100(c) is a cross-sectional view through a line 100C-100C in FIG. 99;

FIG. 101 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 10 of the presentinvention through the sealing parts;

FIGS. 102(a) to 102(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 101, in which FIG. 102(a) is across-sectional view through a line 102A-102A in FIG. 101, FIG. 102(b)is a cross-sectional view through a line 102B-102B in FIG. 101, and FIG.102(c) is a cross-sectional view through a line 102C-102C in FIG. 101;

FIG. 103 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 11 of the presentinvention through the sealing parts;

FIGS. 104(a) to 104(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 103, in which FIG. 104(a) is across-sectional view through a line 104A-104A in FIG. 103, FIG. 104(b)is a cross-sectional view through a line 104B-104B in FIG. 103, and FIG.104(c) is a cross-sectional view through a line 104C-104C in FIG. 103;

FIG. 105 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 12 of the presentinvention through the sealing parts;

FIGS. 106(a) to 106(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 105, in which FIG. 106(a) is across-sectional view through a line 106A-106A in FIG. 105, FIG. 106(b)is a cross-sectional view through a line 106B-106B in FIG. 105, and FIG.106(c) is a cross-sectional view through a line 106C-106C in FIG. 105;FIG. 106(d) is the front view of the structure of the semiconductordevice shown in FIG. 105; and FIG. 106(e) is the side view of thestructure of the semiconductor device shown in FIG. 105;

FIG. 107 is a view of a base surface showing the under surface of thesemiconductor device (CSP) shown in FIG. 105;

FIG. 108 is an enlarged partial view showing the detailed structure ofthe thin film wiring substrate shown in FIG. 89;

FIG. 109 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 13 of the presentinvention through the sealing parts;

FIGS. 110(a) to 110(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 109, in which FIG. 110(a) is across-sectional view through a line 110A-110A in FIG. 109, FIG. 110(b)is a cross-sectional view through a line 110B-110B in FIG. 109, and FIG.110(c) is a cross-sectional view through a line 110C-110C in FIG. 109;

FIG. 111 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 14 of the presentinvention through the sealing parts;

FIGS. 112(a) to 112(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 111, in which FIG. 112(a) is across-sectional view through a line 112A-112A in FIG. 111, FIG. 112(b)is a cross-sectional view through a line 112B-112B in FIG. 111, and FIG.112(c) is a cross-sectional view through a line 112C-112C in FIG. 111.

FIG. 113 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 15 of the presentinvention through the sealing parts;

FIGS. 114(a) to 114(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 113, in which FIG. 114(a) is across-sectional view through a line 114A-114A in FIG. 113, FIG. 114(b)is a cross-sectional view through a line 114B-114B in FIG. 113, and FIG.114(c) is a cross-sectional view through a line 114C-114C in FIG. 113;

FIG. 115 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 16 of the presentinvention through the sealing parts;

FIGS. 116(a) to 116(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 115, in which FIG. 116(a) is across-sectional view through a line 116A-116A in FIG. 115, FIG. 116(b)is a cross-sectional view through a line 116B-116B in FIG. 115, and FIG.116(c) is a cross-sectional view through a line 116C-116C in FIG. 115;

FIG. 117 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 17 of the presentinvention through the sealing parts;

FIGS. 118(a) to 118(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 117, in which FIG. 118(a) is across-sectional view through a line 118A-118A in FIG. 117, FIG. 118(b)is a cross-sectional view through a line 118B-118B in FIG. 117, and FIG.118(c) is a cross-sectional view through a line 118C-118C in FIG. 117;

FIG. 119 is a plan view showing an example of a structure of asemiconductor device (CSP) according to an Embodiment 18 of the presentinvention through the sealing parts;

FIGS. 120(a) to 120(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 119, in which FIG. 120(a) is across-sectional view through a line 120A-120A in FIG. 119, FIG. 120(b)is a cross-sectional view through a line 120B-120B in FIG. 119, and FIG.120(c) is a cross-sectional view through a line 120C-120C in FIG. 119;

FIGS. 121(a), 121(b), 121(c) are diagrams each showing an unconnectedlead in the semiconductor device according to an Embodiment 19 of thepresent invention, in which FIG. 121(a) is a cross-sectional view whenthe unconnected lead is deformed, and FIGS. 121(b), 121(c) arecross-sectional views when the unconnected lead is not deformed;

FIGS. 122(a), 122(b), 122(c) are cross-sections each showing a typicalstructure using a single-layer surface-wired thin film wiring substratein the semiconductor device according to an Embodiment 20 of the presentinvention;

FIGS. 123(a), 123(b), 123(c) are cross-sections each showing a typicalstructure using a two-layer thin film wiring substrate in thesemiconductor device according to Embodiment 20 of the presentinvention;

FIGS. 124(a), 124(b), 124(c), 124(d) are enlarged partial cross-sectionseach showing an example of a lead tip processing sequence in a method ofmanufacturing a semiconductor device according to an Embodiment 21 ofthe present invention, in which FIG. 124(a) shows results beforebonding, FIG. 124(b) shows results during bonding, FIG. 124(c) showsresults after bonding, and FIG. 124(d) shows results after sealing;

FIGS. 125(a), 125(b), 125(c) are enlarged partial cross-sections showinganother example of a lead tip processing sequence in a method ofmanufacturing a semiconductor device according to an Embodiment 21 ofthe present invention, for comparison with the lead tip processingsequence of FIG. 124, in which FIG. 125(a) shows results before bonding,FIG. 125(b) shows results during bonding, and FIG. 125(c) shows resultsafter sealing;

FIGS. 126(a), 126(b), 126(c) are enlarged partial cross-sections showinganother example of a lead tip processing sequence in a method ofmanufacturing a semiconductor device according to Embodiment 21 of thisinvention, for comparison with the lead tip processing sequence of FIG.124, in which FIG. 126(a) shows results before bonding, FIG. 126(b)shows results during bonding, and FIG. 126(c) shows results aftersealing;

FIG. 127 is an elastomer specification table showing examples of colorspecifications of an elastomer (elastic structure) used in asemiconductor device (CSP) according to an Embodiment 22 of the presentinvention;

FIGS. 128(a) to 128(h) are diagrams showing typical elastomercompositions in a semiconductor device according to an Embodiment 23 ofthe present invention;

FIGS. 129(a) to 129(e) are diagrams showing typical elastomercompositions in a semiconductor device according to Embodiment 23 of thepresent invention, in which FIG. 129(a) to 129(d) show a 3-layerstructure, and FIG. 129(e) shows a 5-layer structure;

FIGS. 130(a) and 130(b) show example thicknesses of a skeleton layer andadhesive layers of an elastomer according an Embodiment 24 of thepresent invention;

FIG. 131 is a view of a base surface showing the under surface of thesemiconductor device (CSP) according to an Embodiment 25 of the presentinvention;

FIGS. 132(a), 132(b), 132(c), 132(d) are diagrams showing an examplestructure of a semiconductor device according to an Embodiment 26 of thepresent invention, in which FIG. 132(a) is a base view, FIG. 132(b) is aside view, FIG. 132(c) is a partial cut-away plan view, and FIG. 132(d)is a front view;

FIGS. 133(a), 133(b), 133(c) are diagrams showing the structure of thesemiconductor device shown in FIG. 132, in which FIG. 133(a) is across-sectional view through a line 133A-133A in FIG. 132, FIG. 133(b)is a cross-sectional view through a line 133B-133B in FIG. 132, and FIG.133(c) is a cross-sectional view through a line 133C-133C in FIG. 132;

FIGS. 134(a), 134(b) are enlarged partial cross-sections showing thestructure of the semiconductor device shown in FIG. 133, in which FIG.134(a) is a diagram showing a part D in FIG. 133(b), and FIG. 134(b) isa diagram showing a part E in FIG. 133(c);

FIGS. 135(a) to 135(f) are diagrams showing an example of a method ofmanufacturing a thin film wiring substrate used in the semiconductordevice according to Embodiment 26 of the present invention, in whichFIGS. 135(a), 135(c), 135(e) are partial plan views, and FIGS. 135(b),135(d), 135(f) are respectively cross-sections through lines 135B-135B,135D-135D and 135F-135F;

FIGS. 136(a) to 136(d) are diagrams showing an example of a method ofmanufacturing a thin film wiring substrate used in the semiconductordevice according to Embodiment 26 of the present invention, in whichFIGS. 136(a), 136(c) are partial plan views, and FIGS. 136(b), 136(d)are respectively cross-sections through lines 136B-136B and 136D-136D;

FIGS. 137(a) to 137(f) are diagrams showing an example of a method ofmanufacturing a thin film wiring substrate used in the semiconductordevice according to Embodiment 26 of the present invention, in whichFIGS. 137(a), 137(d) are partial plan views, FIGS. 137(b), 137(e) arerespectively cross-sections through lines 137B-137B and 137E-137E, andFIGS. 137(c), 137(f) are respectively cross-sections through lines137C-137C and 137F-137F;

FIGS. 138(a) to 138(f) are diagrams showing an example of a method ofmanufacturing a thin film wiring substrate used in the semiconductordevice according to Embodiment 26 of the present invention, in whichFIGS. 138(a), 138(d) are partial plan views, FIGS. 138(b), 138(e) arerespectively cross-sections through lines 138B-138B and 138E-138E, andFIGS. 138(c), 138(f) are respectively cross-sections through lines138C-138C and 138F-138F;

FIGS. 139(a) to 139(f) are diagrams showing an example of a method ofmanufacturing a thin film wiring substrate used in the semiconductordevice according to Embodiment 26 of the present invention, in whichFIGS. 139(a), 139(d) are partial plan views, FIGS. 139(b), 139(e) arerespectively cross-sections through lines 139B-139B and 139E-139E, andFIGS. 139(c), 139(f) are respectively cross-sections through lines139C-139C and 139F-139F;

FIGS. 140(a), 140(b), 140(c) are diagrams showing an example of a methodof manufacturing a thin film wiring substrate used in the semiconductordevice according to an Embodiment 27 of the present invention, in whichFIG. 140(a) is a side view, FIG. 140(b) is a plan view, and FIG. 140(c)is a front view;

FIGS. 141(a), 141(b), 141(c), 141(d) are diagrams showing an example ofthe structure of a thin film wiring substrate according to an Embodiment28 of the present invention, in which FIG. 141(a) is a base view, FIG.141(b) is a side view, FIG. 141(c) is a plan view, and FIG. 141(d) is afront view;

FIGS. 142(a), 142(b) are diagrams showing an example of a state whensealing is complete in a manufacturing method according to Embodiment 28of the present invention;

FIGS. 143(a), 143(b), 143(c) are diagrams showing cross-sections throughthe plan view shown in FIG. 143(a), in which FIG. 143(a) is across-section showing the plane 143A-143A, FIG. 143(b) is across-section showing the plane 143B-143B, and FIG. 143(c) is across-section showing the plane 143C-143C;

FIGS. 144(a), 144(b), 144(c) are diagrams showing an example of a statewhen sealing is complete in a manufacturing method according toEmbodiment 28 of the present invention, in which FIG. 144(a) is a planview, FIG. 144(b) is a side view, and FIG. 144(c) is a base view;

FIG. 145 is a schematic diagram of a state when gas is leaving in thesemiconductor device according to Embodiment 28 of the presentinvention;

FIGS. 146(a) to 146(e) are diagrams each showing an example structure ofa semiconductor device according to an Embodiment 29 of the presentinvention, in which 146(a) is a base view, FIG. 146(b) is a side view,FIG. 146(c) is a plan view, FIG. 146(d) is a front view, and FIG. 146(e)is a cross-section through a line 146E-146E in FIG. 146(c);

FIGS. 147(a), 147(b), 147(c) are diagrams showing an example structureof a semiconductor device according to an Embodiment 30 of the presentinvention, in which FIG. 147(a) is a plan view, FIG. 147(b) is a sideview, and FIG. 147(c) is a base view;

FIG. 148 is a partial plan view showing an example of a sealingcompletion state in a method of manufacturing the semiconductor deviceaccording to Embodiment 30 of the present invention;

FIGS. 149(a), 149(b) are diagrams of cross-sections through line149A-149A and line 149B-149B, respectively, of the partial plan viewshown in FIG. 148;

FIGS. 150(a), 150(b) are diagrams each showing an example of a statewhen sealing is complete in a manufacturing method according toEmbodiment 30 of the present invention, in which FIG. 150(a) is a baseview, and FIG. 150(b) is a base view showing a semiconductor chipremoved; and

FIG. 151 is a schematic diagram of a state when gas is leaving in thesemiconductor device according to Embodiment 30 of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A detailed description of the embodiments with reference to theaccompanying drawing illustrations follows:

Embodiment 1

FIG. 1 is a plan view illustrating a semiconductor integrated circuitdevice representing an Embodiment 1 according to the present invention,FIG. 2 is a cross sectional view taken along line 2-2 in FIG. 1, FIG. 3and FIG. 4 are a plan view and a cross sectional view illustrating astate of mounting a semiconductor integrated circuit device to amounting substrate, FIG. 5 is a flow chart illustrating the steps(process) of assembling a semiconductor integrated circuit device, andFIG. 6 to FIG. 58 and FIG. 76 to FIG. 81 are views for comparativeexplanation between the feature of the semiconductor integrated circuitdevice representing the Embodiment 1 of the present invention and asemiconductor integrated circuit device representing a comparativeexample studied by the present inventors. At first, an explanation willbe given as to the constitution of a semiconductor integrated circuitdevice of an Embodiment 1 with reference to FIG. 1 and FIG. 2.

The semiconductor integrated circuit device representing Embodiment 1 ofthe present invention is in the form of a 40 pin ball grid array typesemiconductor package, comprising a semiconductor chip 1 having aplurality of semiconductor elements and a plurality of bonding padsformed on a main surface, and an elastomer 2 (elastic structuralmaterial) bonded on the main surface of the semiconductor chip exceptingfor the portions forming the bonding pads, a flexible wiring substrate 3(wiring substrate) formed with wirings connected at one end to thebonding pads of the semiconductor chip 1, a solder resist 4 (insulationfilm) formed on a main surface of the flexible wiring substrate 3, andbumps 5 (bump electrodes) formed on a main surface of the solder resist4 and connected to the other end of the wirings by way of openings inthe solder resist 4, to constitute a package structure in which thebonding portion of the semiconductor chip 1 is covered by a sealant 6,such as a resin.

The semiconductor chip 1 has, for example, a center pad structure asshown in FIG. 1 in which a plurality of bonding pads 7 (externalterminals) are formed in one row at a central portion in thelongitudinal direction, and the bonding pads are arranged at non-uniformintervals. Predetermined integrated circuits, such as memory circuitsand logic circuits, are formed in the semiconductor chip 1, for example,on a semiconductor substrate, such as made of silicon, and the bondingpads 7 made of a material such as Al are disposed as the externalterminals for such circuits.

The elastomer 2 is made of an elastic material, for example, a siliconeresin, which is formed on the main surface of the semiconductor chip 1,being bisected longitudinally of the chip 1 to provide the portionformed with the bonding pads 7, and is bonded to the main surface of thechip 1 by way of the adhesive 8. The elastomer 2 is provided formoderating stress concentration on the soldering bumps 5 mainly causedby the difference in the heat expansion coefficients of thesemiconductor chip 1 and the package mounting substrate.

The flexible wiring substrate 3 comprises, for example, as shown in FIG.2, a tape 9 as a basic material of the flexible wiring substrate 3(substrate base material) and wirings 10 bonded on the main surface ofthe tape 9 by an adhesive 9′, in which leads 11 on one end of thewirings 10 are connected to the bonding pads 7 of the semiconductor chip1, and bump lands 12 on the other end are connected with the solderingbumps 5. In the flexible wiring substrate 3, the rear face of the tape 9(on the side opposite to the surface formed with the wirings 10) isbonded to the elastomer 2, and the solder resist 4 is formed on the mainsurface of the wirings 10.

The tape 9 constituting the flexible wiring substrate 3 is made of amaterial, for example, a polyimide resin, and a material such as Cu isused as the core material for the wiring 10. A portion of the lead 11serving as one end of the wiring 10 is formed with an Ni plating layerso as to cover the surface of the core material, and an Au plating layeris formed further so as to cover the surface of the Ni plating layer.

The solder resist 4 is made of an insulation material, such as a lightsensitive epoxy resin, and the solder bumps 5 are formed on the mainsurface of the wirings 10 of the flexible wiring substrate 3 by way ofthe openings in the solder resist 4 for a predetermined range of thewirings 10, except for the connection portion connected to the bumplands.

The soldering bumps 5 are made of a material, for example, aPb(60%)-Sn(40%) solder or an alloyed solder mainly composed of Pb—Sn,and is connected to the bump lands 12 of the wirings 10 constituting theflexible wiring substrate 3. The solder bumps 5 are arranged in two rowsin the regions on both side of the bonding pads 7 of the semiconductorchip 1.

The thus constituted semiconductor integrated circuit device is mounted,for example, as shown in FIG. 3 and FIG. 4, as a semiconductorintegrated circuit device of a chip size package 13, for example, aDRAM, together with a semiconductor integrated circuit device of QFPtype package 14, onto a mounting substrate 15, which is made, forexample, of glass or epoxy, on a memory card and can be retractablymounted with respect to portable equipment, such as a portable telephoneor a handy type personal computer by way of external connectionterminals 16.

For the function of the Embodiment 1 of the present invention, anoutline of the steps of assembling the semiconductor package will beexplained on the basis of the process flow shown in FIG. 5.

At first, before assembling the semiconductor package, wirings 10 areformed on the tape 9, the flexible wiring substrates having the leads 11formed by etching a portion of the wirings 10. Further, the elastomer 2,the semiconductor chip 1 formed with predetermined integrated circuitsand provided with the bonding pads 7 as external terminals, the sealant6, and flux and solder forming the solder balls 17 are provided.

The flexible wiring substrate 3 can be prepared, for example, astypically represented by the technique of a TAB (Tape Automatic Bonding)tape, by bonding a thin metal foil such as Cu on a tape 9 made of apolyimide resin by means of an adhesive, forming a required pattern byphotoresist on the metal foil using a photographic technique, thenforming a desired wiring pattern 10 by etching (including also leads 11)and, further, applying Ni—Au plating treatment to the surface thereof,for example, by an electric field plating method.

Then, for example, the elastomer 2 is formed by printing to a thicknessof 50 to 150 μm on the tape 9 of the flexible wiring substrate 3, and asilicone type adhesive 8 is coated and printed on the surface of theelastomer 2 (steps 501, 502). The elastomer 2 is not always printed, butan elastomer previously formed into a film-shape may be cut into apredetermined shape and bonded to the rear face of the tape 9 by meansof the adhesive 8.

Further, the leads 11 at one end of the wirings 10 of the flexiblewiring substrate 3 and the bonding pads 7 of the semiconductor chip 1are aligned such that their relative positions coincide with each other,and the semiconductor chip 1 is appended by adhesion to the elastomer 2printed on the tape 19 of the flexible wiring substrate 3 (step 503).

Then, the semiconductor chip 1 and the tape 9 of the flexible wiringsubstrate 3 in a state appended by way of the elastomer 2 are turnedupside down in the lead bonding step, the lead 11 is driven down on thebonding pad 7 of the semiconductor chip 1 while being deformed into aS-shaped configuration by a bonding tool 18, as shown by the crosssection in FIG. 2, and the lead 11 and the bonding pad 7 are connected,for example, by a method of supersonic thermal press bonding (step 504).

Successively, in the sealing step, the lead bonding portion of thebonding pad 7 of the semiconductor chip 1 and the lead 11 of theflexible wiring substrate 3 are resin encapsulated, for example, bycoating a sealant 6, such as an epoxy resin, from a dispenser 19 tothereby enhance the reliability at the junction portion between thesemiconductor chip 1 and the flexible wiring substrate 3 (step 505).

Subsequently, in the cutting step for the flexible wiring substrate 3,the outer edge portion of the tape 9 is cut along a position somewhatoutside the edge of the semiconductor chip 1, to form a package outershape of CSP (Chip Size Package or Chip Scale Package) (step 506).

Then, in the bump attaching step of the solder bump 5, the bump 5 isformed by joining a solder ball 17 to the corresponding bump land 12 ofthe wirings 10 of the flexible wiring substrate 3 to form the bump 5and, finally, by way of the selection and marking, the step ofassembling the semiconductor package in the Embodiment 1 according tothe present invention is finished (step 507, 508).

In the step of assembling the semiconductor package, the order of thetape cutting step (step 506) and the bump attaching step (step 507) maybe reversed.

Thus, the Embodiment 1 has a semiconductor package structure in whichbonding pads 7 are arranged concentrically in one row along a centralportion of the semiconductor chip 1, and the solder bumps 5 are disposedat the inside of the outer circumference of the semiconductor chip 1connected by way of the wirings 10 of the flexible wiring substrate fromthe bonding pads 7.

Now, the feature of the package structure for the semiconductorintegrated circuit device of the Embodiment 1 will be explained bycomparison with a package structure formed by a technique studied by thepresent inventors including the structure and the process with referenceto FIG. 6 to FIG. 58 successively.

1. Surface Wiring Structure (A Structure in which the Elastomer isFormed on the Wiring Substrate on the Side of the Tape and the BumpElectrodes are Formed on the Side of the Wirings)

To assist in providing technical explanation of the surface wiringstructure, FIG. 6 is a cross sectional view of a main portionillustrating the surface wiring structure, FIG. 7 is a cross sectionalview of a main portion illustrating the rear face wiring structure (astructure in which bump electrodes are formed to the wiring substrate onthe side of the tape and the elastomer is formed on the side of thewirings) and FIG. 8 is a cross sectional view of a main portionillustrating wirings on both surfaces.

The package structure of the Embodiment 1 is a so-called “surface wiringstructure” as shown in an enlarged scale in FIG. 6, in which anelastomer 2 is bonded to a flexible wiring substrate 3 on one side of atape 9 (on the side facing the semiconductor chip 1) and a solder resist4 and a bump electrode 5 are formed on the other side of the wirings 10.On the other hand, there is a technique studied by the present inventorwhich may be referred to as a so-called “rear face wiring structure”, asshown in FIG. 7, in which an elastomer 2 is bonded on one side of thewiring 10 and a solder bump 5 is formed on the other side of the tape 9.In FIG. 6, an Au plating 11 a is formed, for example, by an electricfield plating on the surface of a lead 11 on one end and on the surfaceof a land 12 on the other end of the wiring 10.

In the rear face wiring structure described above with reference to FIG.7, a through hole 12 b for joining the bump 5 is formed, for example, bypunching out an opening in the tape 9, which is made of a material suchas a polyimide resin, whereas in the surface wiring structure of theEmbodiment 1, as seen in FIG. 6, a solder resist 4 made of a materialsuch as a light sensitive epoxy resin is coated on the main surface ofthe wiring 10, and a connection hole 12 a of a desired size is formed ata desired position by a photographic process, such as exposure anddevelopment, so that the following advantages can be expected.

(1) Since the opening for the solder bump 5 is formed by exposure anddevelopment of the solder resist 4, the fabrication accuracy for thehole diameter can be improved compared with a case of puncturing anopening in the tape 9 of the flexible wiring substrate 3 in the rearface wiring structure by machining.

(2) While the minimum thickness of the tape 9, in practice, is about 50μm, the solder resist 4 can be coated to a thickness of about 10 to 20μm stably depending on the coating condition, so that a smaller solderball 17 can be joined satisfactorily.

For example, in a case of forming a solder bump of about 30 μm diameter,which is less than the thickness of the tape 9, the aspect ratio of thethrough hole is excessively large in the rear face wiring structure,thereby possibly resulting in a connection failure. On the other hand,the aspect ratio can be lowered to cope with such a problem in thesurface wiring structure.

(3) Since the pitch of the solder bumps 5 can be made smaller in thesurface wiring structure as compared with the rear face wiringstructure, a semiconductor package having output terminals for thesolder bumps arranged with a higher density can be obtained.

(4) Since an elastomer 2 is disposed on the flat surface at the back ofthe tape 9, the elastomer 2 can be mounted (coated or appended) in avoidless manner stably with a high accuracy. Further, since the size andthe shape of the elastomer 2 are stabilized, the step of bonding thesemiconductor chip 1 is also stable, thereby making it possible toconduct assembling at a higher yield.

As described above, the technique of forming the rear face wiringstructure results in problems, such as in the formation of the openingin the tape 9 of the flexible wiring substrate 3 and in the bondabilitybetween the wirings 10 of the flexible wiring substrate 3 and theelastomer 2, whereas such problems can be solved by adopting the surfacewiring structure as provided in the Embodiment 1.

Further, in the wiring structure of the flexible wiring substrate 3, itis possible to use a flexible wiring substrate 3 having a double facewiring structure, for example, as shown in FIG. 8, that is, havinglayered wirings on both surfaces of the tape 9, in addition to thesingle face wiring structure as shown in FIG. 6, and it can be appliedfurther to three or more layered wiring structures.

In the example of FIG. 8, a first wiring 20 is used as a signal wiringwhile the second wiring 21 is used as a ground plane, in which thesecond wiring 21 and the bump 5 or the first wiring 20 are electricallyconnected by way of a via hole 22. Such a structure has the advantage ofobtaining an excellent electric characteristic, for example, from thepoint of view of noise resistance.

2. Optimization of Tape Edge Position Relative to Elastomer

To assist in providing a technical explanation of the optimization oftape edge position relative to the elastomer, FIG. 9 is a plane viewillustrating window openings, FIG. 10 is a cross sectional viewillustrating a window opening in FIG. 9 and FIG. 11 is a cross sectionalview for assisting in the explanation of the size of the window openingportion and the edge portion of the semiconductor chip.

The package structure of the Embodiment 1, as shown in FIG. 9, has a BGA(Ball Grid Array) structure in which the solder bumps 5 are arranged ina matrix on the main surface of the flexible wiring substrate 3. In thisexample, as shown in FIG. 10, the semiconductor 1 has a center padarrangement in which a window opening portion 23 is disposedlongitudinally at a central portion, and the portion and the peripheraledge of the semiconductor chip 1 are resin capsulated by the sealant 6to attain a structure of high moisture proofness and reliability in thefinal structure.

By the way, in the technique studied by the present inventor, when theend of the elastomer 2 (on the side of the window opening 23) is broughtcloser to the edge of the tape 9, that is, if the length L1 between theend of the elastomer 2 of the semiconductor chip 1 on the side of thebonding pad 7 and the end of the tape 9 is reduced, contamination to thelead 11 results due to a bleeding ingredient and volatile ingredient ofthe elastomer 2.

On the other hand, if the length L1 is made larger, that is, if theelastomer is excessively retracted (i.e., recessed) from the edge of thetape 9, the length L2 between the end of the elastomer 2 and the solderbump 5 is reduced, and since the elastomer 2 is not present below theinnermost portion of the solder bump 5, this may possibly increase thevariation in the height of the solder bump 5 or widen the encapsulationregion for the window opening 23, making it difficult to fill in thesealant 6.

On the other hand, in the Embodiment 1, these problems can be solvedsimultaneously by selecting an appropriate length for L1 so as to setthe end of the elastomer 2 at an optimal position between the end of thetape 9 and the solder bump 5.

That is, in order to eliminate the foregoing problems related to thewindow opening 23, the length L1 is defined as indicated below. Forexample, in this embodiment, the printing accuracy of the elastomer 2 isdefined as about ±100 μm. Accordingly, if the length L1 is less than 100μm, since it may extend outside of the tape 9 due to a printingdeviation, it must be greater than the printing accuracy (100 μm) at theleast.

Further, since there is no problem from contamination to the lead 11 bya bleeding ingredient or volatile ingredient of the elastomer 2 if it isactually spaced by about 300 μm from the actual edge, the length L2 isset, for example, at 300 μm as a minimum. However, a design with aminimum value of about 100 μm is possible if an elastomer 2 of lesscontamination and bleeding is used or a countermeasure, for example,cleaning of the contamination, is adopted.

As described above, contamination to the lead 11 caused by bleedingingredients or volatile ingredients of the elastomer 2 can be prevented,the variation in the height of the solder bumps 5 can be made stable andthe sealing region of the window opening 23 can be filled with ease byselecting an appropriate length L1 as provided in the Embodiment 1.

3. Optimization of the Outer Size of the Package

To assist in providing a technical explanation of the optimization ofthe outer size of the package, FIG. 11 is a cross sectional view forexplaining the size of the window opening and the edge portion of thesemiconductor chip, FIG. 12 is a cross sectional view illustrating aconcave portion of the elastomer after printing and FIG. 13 is a crosssectional view illustrating warp in the tape after appending asemiconductor chip.

For example, in the technique studied by the present inventor, lookingto FIG. 11 and assuming that the distance between the end of thesemiconductor chip 1 on the outer circumference of the package and theend of the tape 9 of the flexible wiring substrate 3 is M1 and thedistance between the end of the elastomer 2 and the end of the tape 9 isM2, the following problems are present:

(1) If M1<0, since the outermost circumference of the package isrepresented by the wall of the semiconductor chip 1, there is a greatpossibility of inducing cracks in the semiconductor chip 1 during theassembling step, particularly upon insertion and withdrawal of the chipfrom a receptacle, during tray transportation and the like.

(2) If M1<0, M2>0, since the circuit surface of the semiconductor chip 1will be exposed to the outside, a problem may be caused which affectsthe reliability and the sealing for preventing this, although thispossibly leads to an increase of the fabrication steps.

(3) If M1−M2<0, peripheral protrusions of the elastomer 2 afterprinting, as shown in FIG. 12, interferes with the bonding portion ofthe semiconductor chip 1, as shown in FIG. 13, so as to cause bondingfailure upon appending, reducing the flatness of the flexible wiringsubstrate 3 and causing a reduction of the reliability.

(4) If M2=0, it is necessary to cut the elastomer 2, which causes aproblem due to the difficulty of the cutting.

On the other hand, in the Embodiment 1, the foregoing problems can beovercome by determining the relationship for the distance between theend of the semiconductor chip 1 or the end of the elastomer 2 and end ofthe tape 9 as: M1>M2>0. That is, in the explanatory view illustratingthe edge portion of the package in FIG. 11, since the cutting error inthe tape cutting step for determining the final outer shape is about 100μm, it is desirable to ensure that M2 is more than 100 μm in order thatthe cutting jig does not reach the elastomer 2.

By the way, the cross sectional shape after forming the elastomer 2 byprinting and hardening the same by baking is as shown in FIG. 12, whichshows that a peripheral portion tends to be higher as a result of beingpulled by the mask upon leaving the plate after printing in a case of amaterial having a thixotropic property which is higher to some extent.For example, if the semiconductor chip 1 is appended to the elastomer 2under the condition that M1<M2 so that the end of the semiconductor chipextends past the end of the elastomer 2, a problem occurs in that thesurface of the tape 9 warps to conform to the cross sectional shape ofthe elastomer 2, as shown in FIG. 13.

In order to prevent this, it is effective to eliminate the highperipheral portion of the elastomer 2 at the outside of thesemiconductor chip 1 by setting M1>M2. For instance, since the width ofthe protrusion is about 200 μm, it is desirable for (M1−M2) to be 240 μmand the distance M1 to be about 360 μm in view of the distance M2=100 μmbeing provided for the cutting property.

Cutting the tape 9 at the outer circumference as described aboveprovides advantages in that the outer shape error is reduced, andperipheral jigs such as a receptacle or a tray need not be changed tochange the size to some extent of the semiconductor chip 1.

As described above, in the Embodiment 1, it is possible to avoidcracking and chipping of the semiconductor chip 1 to improve the cuttingmargin during the cutting step. Further, the circuit surface of thesemiconductor chip 1 can be entirely disposed below the elastomer 2 toprovide the advantage of improving the moisture proofness andeliminating the requirement for sealing the outer circumferentialportion.

4. Planar S-Shaped Lead

To assist in providing a technical explanation of the planar S-shapedlead, FIG. 14 is a plan view illustrating a planar S-shaped lead, FIG.15 is a cross sectional view as seen in the direction of arrow B in FIG.14, FIG. 16 is a cross sectional view as seen in the direction of arrowA in FIG. 14, FIG. 17 is a cross sectional view illustrating the traceof a bonding tool upon forming a standard S-shaped lead and FIG. 18 is across sectional view illustrating the trace of a bonding tool uponforming a planar S-shaped lead.

The S-shaped configuration is such that the length of a lead 11 at oneend of a wiring 10 is substantially longer than the linear distancebetween a pad 7 of a chip 1 and the edge portion 11 b of the tape 9, sothat stresses on the lead 11 can be reduced.

For example, in the technique of forming a standard S-shaped lead 24 asstudied by the present inventor, the lead which is employed is a linearnotch lead or a beam lead, as shown by the dotted line in FIG. 14, andin order to form a sag (S-shaped configuration) sufficient to withstandthermal deformation during bonding, as shown by a fine line in FIG. 15,it is necessary to employ a motion along a special bonding tool trace 25which involves first driving down the lead 11 just above thesemiconductor chip 1, then laterally displacing the lead and then againdriving it down onto the bonding pad 7, which operation may require aspecial wire bonder.

On the other hand, in the Embodiment 1, the foregoing problem can besolved by preparing the lead 11 of the wiring 10 so that it does nothave a linear shape, but is a planar lead 26 of a S-shaped configurationin which the base portion of the wiring 10 and the bonding portion atthe top end are previously displaced at least by more than the width ofthe lead 11, as shown in FIG. 14, upon forming the wiring 10 on the tape9 of the flexible wiring substrate 3.

As described above, by such forming of the planar S-shaped lead 26, alead having a stable and suitable S-shaped configuration can be formedby a bonding tool trace 25 by simply driving down a typical wire bonder,as shown in FIG. 18, since a sag due to the original planar S-shapedconfiguration is formed as shown in FIG. 16, although a straightenedshape as shown in FIG. 15 is formed.

Thus, a planar S-shaped lead 26 of stable S-shaped configuration can befound with no requirement for a soft-modified special wire bonder and,further, an effect for shortening the contact time upon bonding can alsobe expected since the bonding tool trace 25 can also be simplified.

5. Beam Lead

To assist in providing a technical explanation of the beam lead, FIG. 19is a plan view for explaining a notch lead and a beam lead, FIG. 20 is aplan view illustrating a notch lead in a portion A of FIG. 19 and FIG.21 is a plan view illustrating a beam lead.

For example, in the technique studied by the present inventor, as shownin FIG. 20, which is an enlarged view of the lead 11 in FIG. 19, thelead 11 is formed with a notch 27, for example, of a V-shaped cut at acutting portion. A portion slightly inside of the notch 27 is drivendownwardly by a bonding tool 18 upon bonding, to cut the lead 11 at theportion of the notch 27. However, the width of the notch 27 changes dueto varied etching for the wiring 10 in the manufacturing step forproducing the flexible wiring substrate 3, leading to the possibilitythat the lead will not be cut upon bonding.

Further, even if it is cut, there still may be a problem in that thelead may be cut at a portion different from the desired notch 27, or thenotch may be too narrow resulting in the lead being disconnected beforethe plating step of the flexible wiring substrate 3, so that the platingcan not be accomplished.

On the other hand, in the Embodiment 1, as shown in FIG. 21, the problemupon cutting the lead 11 as described above can be overcome by formingthe lead with a cantilever beam structure, namely, a so-called beam lead28 in which one end is fixed to the tape 9 of the flexible wiringsubstrate 3 and the other end as the cutting side formed with the notch27 is left open.

6. Passivation Size for the Periphery of the Bonding Pad

To assist in providing a technical explanation of the size of thepassivation film at the periphery of the bonding pad, FIG. 22 is a crosssectional view illustrating a lead bonding portion, FIG. 23 is a planview illustrating a lead bonding portion, FIG. 24 is a cross sectionalview illustrating a tool landing point at the portion in FIG. 22 in anenlarged scale, FIG. 25 is a cross sectional view illustrating a bondingportion improved for the size of the passivation opening and FIG. 26 isa plan view illustrating a bonding portion of a two way lead.

In a memory chip typically represented by a DRAM or the like, apassivation film 29 made of a polyimide type resin is formed on the chipfor preventing soft errors caused by a-rays.

For example, in the technique studied by the present inventor, since thelead 11 is first driven downwardly just above the semiconductor chip 1,then displaced laterally and again driven downwardly on the bonding pad7 of the semiconductor chip 1, as shown by the bonding tool trace 25 inthe bonding sequence in FIG. 22, FIG. 23 and FIG. 24, there is thepossibility of a problem in that the passivation film 29 on thesemiconductor chip 1 or the semiconductor chip 1 therebelow may undergodamage during the first driving down operation, or ingredients of thepassivation film 29 may be deposited to contaminate the bonding portionon the lower surface of the lead 11 to degrade the bondability.

On the other hand, in the Embodiment 1, the foregoing problems can besolved by setting the distance L3 from the edge of the bonding pad 7 tothe edge of the passivation film 29 on the side of the bonding pad 7, asseen in FIG. 22, FIG. 23, and FIG. 24, such that the passivation opening30 is extended and enlarged, whereby the lead 11 does not interfere withthe passivation film 29 at least on the side thereof where the bondingtool 18 is driven down, resulting in an improvement, as shown in FIG.25.

That is, in FIG. 24, the size L3 is about 25 μm in an example of asemiconductor chip 1, for example, a memory device. In this regard,since the size of the bonding pad 7 is 100 μm square and the size of thetop end of the bonding tool 18 is equal to or less than that, thedistance L3 of the passivation film 29 from the pad 7, as seen in FIG.25, is desirably, for example, more than 125 μm.

As described above, a suitable bonding property can be attained withoutthe risk of damage to the passivation film 29 on the semiconductor chip1 or to the semiconductor chip 1 or without deposition of ingredients ofthe passivation film 29 onto the bonding portion at the lower surface ofthe lead 11 which could result in contamination.

Further, in a case where the leads 11 extend in both directions, theproblem can also be coped with similarly by enlarging the distance fromthe opening edge of the bonding pad 7 to the edge of the passivationfilm 29 on the side of the bonding pad 7 at least on the side where thebonding tool is driven down. Enlargement of the space between the edgescauses no problem even if applied to the opposite side to such an extentas to avoid exposing the circuit surface of the semiconductor chip 1.

7. Improvement of the Anchor Wiring

To assist in providing a technical explanation of the improvement of theanchor wiring, FIG. 27 is a plan view illustrating a standard anchorwiring and FIG. 28 is a plan view illustrating an improved anchorwiring.

For example, in the technique studied by the present inventors, in apattern of a standard anchor wiring 31 on the terminal end of a notch,as shown in FIG. 27, if the notch 27 is formed to be smaller than adesigned value, there is a possibility that the lead will not be cut atthe portion of the notch 27, but the bonding strength between the wiring10 and the tape 9 ahead of the notch in the standard anchor wiring 31may not be sufficient to prevent a portion of the standard anchor wiring31 to be peeled from the tape 9.

On the other hand, in this Embodiment 1, the bonding strength betweenthe wiring 10 and the tape 9 can be increased to obtain a stable cuttingperformance of the notch 27 by providing an enlarged anchor wiring 32for enlarging the effective area in the portion for the anchor wiring atthe terminal end as shown in FIG. 28.

That is, the following improved examples of enlarged anchor wirings 32are shown in FIG. 28.

(1) An enlarged anchor wiring 32 is connected to a bump land 12 to anopposing wiring 11.

(2) Enlarged anchor wiring 32 is extended longitudinally in a vacantspace in the wirings 11.

(3) Enlarged anchor wiring 32 is extended laterally in a vacant space inthe wirings 11.

(4) Adjacent extended anchor wirings 32 are connected with each other.In each of the examples, the cutting performance of the notch 27 can bestabilized by the increase of the adhesion strength between the wiring10 and the tape 9 by increasing the effective area of the portion of theenlarged anchor wirings 32.

8. Wide Elastomer Structure

To assist in providing technical explanation of the wide elastomerstructure, FIG. 29 is a perspective view illustrating a structure of astandard elastomer, FIG. 30 is a perspective view illustrating the stateof appending a semiconductor chip to a standard elastomer, FIG. 31 is aperspective view illustrating the structure of a wide elastomer, FIG. 32is a perspective view illustrating the state of appending asemiconductor chip to the wide elastomer and FIG. 33 is a crosssectional view illustrating the state of appending a semiconductor chipto the wide elastomer.

In the technique studied by the present inventors, the elastomer isbonded on both sides of a bonding pad 7 of a semiconductor chip 1 and,in a structure using a standard elastomer 33, as shown in FIG. 29 andFIG. 30, there is a possibility that warping will occur in the flexiblewiring substrate due to the effect of peripheral protrusions in astructure in which the surface of the elastomer 2 is smaller than thatof the semiconductor chip 1, as shown in FIG. 13, and that the warpingbrings about a problem, for example, during the forming of the solderbumps 5 and the mounting of the substrate.

On the other hand, in the structure of a wide elastomer 34 which islarger than the outer size of the semiconductor chip 1 in the embodimentas shown in FIG. 31, the peripheral protrusions of the wide elastomer 34are outside of the edges of the semiconductor chip, as shown in FIG. 32and FIG. 33, after appending the semiconductor chip 1, and since thesemiconductor chip 1 is bonded substantially to a flat portion of thewide elastomer 34, warping of the flexible wiring substrate 3 can beavoided.

Further, as shown in FIG. 33, since a wide coating area of an adhesive 8can be employed, the portion in which the adhesive 8 is not provided andwhich is left unbonded is reduced in size, and since the adhesive willextrude uniformly at the periphery of the semiconductor chip 1 to forman adhesive bead 35, it is possible to constitute a package of excellentmoisture proofness and reliability without applying peripheral sealing.

More particularly, the width of the protrusions at the periphery of thewide elastomer 34 is, for example, about 200 to 300 μm depending on thephysical property of the material and, accordingly, the wide elastomer34 extends over a larger range at the entire circumference at least bymore than the protrusion width afforded by the chip size of thesemiconductor chip 1, as shown in FIG. 33 in the Embodiment 1.

Further, while the flatness is improved by forming the wide elastomer 34sufficiently large, if the tape 9 is to be cut just at the outercircumference of the semiconductor chip 1, the tape 9 will be cuttogether with the wide elastomer 34 along a cutting line 36, which isnecessary to define the package outer shape.

As described above, by using the wide elastomer 34 which is larger thanthe outer size of the semiconductor chip 1, warping of the flexiblewiring substrate 3 can be suppressed, and the bondability of thesemiconductor chip 1 can be made stable to improve the moistureproofness and the reliability of the package.

9. Groove-Filling Technique of the Elastomer

To assist in providing a technical explanation of the groove-fillingtechnique of the elastomer, FIG. 31 and FIG. 32 are perspective viewsillustrating the structure of the wide elastomer and the state ofappending the semiconductor chip as described above, FIG. 34 is aperspective view illustrating the structure after appending asemiconductor chip to a standard elastomer, FIG. 35 is a cross sectionalview thereof, FIG. 36 is a perspective view illustrating a structureafter appending a semiconductor chip to a wide elastomer, FIG. 37 is across sectional view thereof, FIG. 38 is a cross sectional viewillustrating the concept of metal mask printing, FIG. 39 is a plan viewillustrating a metal mask of a standard elastomer, FIG. 40 is a planview illustrating a metal mask of a wide elastomer, FIG. 41 is a planview illustrating a printed shape of a wide elastomer having pluralbridge portions and FIG. 42 is a plan view illustrating a pottingposition for groove-filling of the wide elastomer.

For example, in the structure of a standard elastomer 33 as shown inFIG. 34 and FIG. 35, in the technique studied by the present inventor,when an elastomer is formed by printing using a metal mask 37, as shownin FIG. 39, in the structure of the standard elastomer 33 shown in FIG.34 and FIG. 35, since a bridge portion 39 is always present across theprinting area opening 38 of the metal mask 37 shown in FIG. 39, a groove40 (space) surrounded by walls of the semiconductor chip 1 and theelastomer is present below the tape suspended portion.

Accordingly, when the window opening 23 (FIG. 9) is resin-encapsulatedin a structure in which the groove 40 remains at the ends of the spacedefined by the semiconductor chip 1 and the elastomer, the sealant 6will leak through the groove 40, and so it is necessary to previouslyseal the open end portions by a method such as separate potting and thenseal the window opening 23.

As described above, the concept of printing by use of a metal mask 37 isdesigned to form the elastomer for a desired range to a desiredthickness, by positioning and disposing a metal mask 37 having aprinting area opening 38 at a predetermined position with respect to aflexible wiring substrate 3, only for the printed portion as shown inFIG. 39 in the case of the standard elastomer 33 and as shown in FIG. 40in the case of the wide elastomer 34.

Accordingly, in the Embodiment 1, the wide elastomer 34 described aboveand shown in FIG. 31 is printed by a metal mask 37 as shown in FIG. 40,in which a groove 40 surrounded by the walls of the semiconductor chip 1and the elastomer 2 can be narrowed by printing the elastomer having arestricted bridge portion 39 for the printing area opening 38 of themetal mask 37. For example, the minimum value for the width of thegroove 40 determined by the strength of the bridge portion 39 of themetal mask 37 is about 200 μm.

Further, in a case of a structure in which the semiconductor chip isappended to the elastomer by coating the adhesive 8 on the main surfaceof the elastomer 2, if the adhesive 8 is coated in a sufficient amount,excessive adhesive 8 will fill the groove 40 in response to the pressurecreated upon appending to make the window opening 23 a closed space, sothat the window opening 23 can be sealed without applying sealing.

Further, the groove-fillage can be improved by restricting the bridgeportion 39 of the metal mask 37 thereby narrowing the groove 40, butthis results in a side effect of lowering the strength of the metal mask37. However, by providing a plurality of bridge positions on one side toproduce the construction as shown in FIG. 41, the strength of the metalmask 37 can be improved without changing the width of the groove 40although the number of the grooves 40 is increased.

Further, with an aim toward improving the groove-fillage, as shown inFIG. 42, when resin, adhesive or the like is potted, for example, at thepotting position 42 of the groove 40 of the elastomer to form a stoppingdam for the sealant flow just before appending the semiconductor chip 1,the groove-fillage can be improved still further.

Further, in a case of filling by potting before sealing the windowopening 23 after appending and bonding of the semiconductor chip as inthe technique studied above, the sealing performance can be improvedoutstandingly by restricting the width of the groove 40.

As described above, the groove-fillage can be improved, particularly, byrestricting the bridge portion 39 of the metal mask 37 thereby narrowingthe groove 40 of the elastomer and, further, the groove-fillage can beimproved even more by previously forming a stopping dam for the sealantflow to the potting position 42.

10. Inner Lead Bonding Technique

To assist in providing an explanation of the inner lead bondingtechnique, FIG. 43 is a cross sectional view illustrating a bondingportion produced by a standard lead bonding, FIG. 44 is a crosssectional view illustrating a bonding portion produced by using a studbump, FIG. 45 and FIG. 46 are a cross sectional view and a plan view,respectively, illustrating a lead connection using soldering, FIG. 47and FIG. 48 are a cross sectional view and a perspective view,respectively, illustrating a lead connection using a solder or Au ball,FIG. 49 is a cross sectional view illustrating a connection using an Alor solder wire and FIG. 50 is a cross sectional view illustrating aconnection using an Au wire.

For example, in the technique studied by the present inventor, a lead 11on which Au plating is provided is directly driven onto a bonding pad 7and thermally press bonded using supersonic waves. In this case, if thebonding condition is poor or the shape of the bonding tool 18 isinadequate, there is the possibility of a problem in that the bondingstrength is low or the bonding pad for a portion therebelow is subjectto damage.

On the contrary, in the Embodiment 1, the problems, for example, ofbondability or damage caused by the bonding condition and the shape ofthe bonding tool 18 as described above can be overcome by adopting thefollowing feature for the bonding state.

That is, FIG. 44 shows an example of using a stud bump 43. This examplehas a feature of using a semiconductor chip 1 having the stud bump 43formed previously by a plating method or a ball bonding method onto abonding pad 7 of the semiconductor chip 1, causing the bondability to beimproved and, further, preventing damage to the bonding pad.

Further, FIG. 45 and FIG. 46 are examples of a connection for the lead11 using solder and showing a connection state in which the lead 11 issurrounded with solder 44. This example concerns a technique forconnecting a bonding pad 7 comprising Al or the like of thesemiconductor chip 1 and an electrode of the tape 9 such as TAB as a CSPsubstrate. A method of feeding the solder in this example includes amethod of connecting the solder 44 with the bonding pad 7 of thesemiconductor chip 1 using the tape 9 on which the solder 44 is alreadypresent so as to surround the lead 11.

For the connection method, it is desirable for the shape of the solder44 provided on the tape 9, such as a TAB, to be made as flat as possibleat the surface in contact with the bonding pad 7 of the semiconductorchip 1 in the connection method by pressurizing and heating using abonder. Further, in a connection method using a reflow furnace, solderpaste or flux is provided at the surface of the bonding pad 7 of thesemiconductor chip 1 so as to be in contact with the solder 44 of thetape 9, such as a TAB.

Then, in the case of feeding the solder 44 using solder paste, thesolder paste may be provided at the surface of the bonding pad 7 of thesemiconductor chip 1 by printing or by using a syringe. In this case,the tape 9, such as a TAB, may be bonded previously or subsequentlyproviding that the lead 11 of the tape 9 is in contact with the solder44 when the tape 9 is bonded to the semiconductor chip 1.

Further, FIG. 47, FIG. 48 show a connection technique having a featureof connecting a lead 11 of a tape 9, such as a TAB, onto a bonding pad 7of a semiconductor chip 1 by using a stud bump, such as a solder or Auball 45.

Further, FIG. 49 shows an example of connecting a wiring 10 of aflexible wiring substrate 3 and a bonding pad 7 of a semiconductor chip1 by using an Al or solder wire 46. Further, FIG. 50 shows an example ofconnecting a wiring 10 of a flexible wiring substrate 3 and a bondingpad 7 of a semiconductor chip 1 by using an Au wire 47. In theconnection examples, the connection is enabled not by way of the innerlead bonding, such as a TAB, but under the concept of a typical wirebonding.

11. Lead Design Technique Capable of Forming an S-Shape With No ToolReturn

To assist in providing an explanation of the lead design techniquecapable of forming an S-shape with no tool return, FIG. 17 is a crosssectional view illustrating a trace of a bonding tool upon forming astandard S-shaped lead as explained previously, FIG. 51 is a perspectiveview for explaining the lead design, FIG. 52 is a perspective viewillustrating deformation of a lead after bonding, FIG. 53 is a chartillustrating a relationship between a lead size and a bending stressratio and FIG. 76 to FIG. 80 are cross sectional views illustrating thedeformed shape of a lead in accordance with the bending stress ratio.

More particularly, as explained also in connection with the techniquefor the planar S-shaped lead 26 in the technique studied by the presentinventor, it is necessary for forming the S-shaped configuration of thelead 11 shown in FIG. 17, to laterally displace the bonding tool 18,namely, a special bonding tool trace 25 including a tool return isrequired.

On the contrary, in the Embodiment 1, if the size of a lead 11 shown inFIG. 51 is defined, for example, as shown in FIG. 53, the bending stressratio α will fall within a desired range of from 1.2 to 1.5 and asuitable S-shaped configuration for the lead 11 as shown in FIG. 52 canbe formed by merely driving down the bonding tool 18 vertically with notool return. In FIG. 52, there are shown a tape end 48, an end 49 on theside of the tape and an end 50 on the side of the chip.

For example, in the example of embodiment (1), the bending stress ratioα=1.26 at the size: taper length L1=100 μm, wiring length L2=380 μm,taper width b1=65 μm, lead width b2=38 μm and lead thickness h=18 μm. Inthe same manner, the ratio is 1.25 in the embodiment (2), 1.26 in theembodiment (3), 1.31 in the embodiment (4) and 1.46 in the embodiment(5).

On the contrary, in the studied technique, at the size: taper lengthL1=100 μm, wiring length L2=280 μm, taper width b1=60 μm, lead widthb2=38 μm and lead thickness h=18 μm, the bending stress ratio α is 1.02,for example, in the example (1) and 1.13 in the example (2) which is outof the range of 1.2 to 1.5.

As described above, since the bending stress is concentrated to anintermediate portion of the lead 11 in the wiring operation within therange of the bending stress ratio α from 1.2 to 1.5, a moderatelydistorted satisfactory wiring state is attained. On the other hand, ifthe bending stress ratio α is less than 1.2 as in the studied technique,since the bending stress is concentrated at the tape end 48 of the lead11, it results in a stiffened state. Further, if the ratio exceeds 1.5,the bending stress is concentrated only at the intermediate portion ofthe lead 11 resulting in a state of a small radius of curvature whichcan not be said to be a satisfactory wiring state.

FIG. 76 to FIG. 80 show the deformed shape of the lead in accordancewith the bending stress ratio α concretely. At first, when the bondingtool 18 is merely driven down vertically to contact the lead of initialshape before wiring shown in FIG. 76, since the bending stress isconcentrated on the tape end 48 of the lead 11, for example, in thewiring operation at α<0.9, an extremely stiffened wiring state is formedas shown in FIG. 77. Accordingly, since high repeating stresses areexerted on the lead 11 during the temperature cycle after wiring, thefatigue life is extremely shortened.

Further, since the bending stress is concentrated at the tape end 48 ofthe lead 11 in the wiring operation at 0.9≦α<1.2 as in the techniquestudied by the present inventor, a somewhat stiffened wiring state isformed as shown in FIG. 78. Accordingly, since high repeating stressesare exerted on the lead 11 during the temperature cycle after thewiring, fatigue life is shortened.

On the contrary, since the bending stress is concentrated at anintermediate portion of the lead 11 during the wiring operation at1.2≦α<1.5 as in the Embodiment 1, a moderately distorted wiring state asshown in FIG. 79 is formed. Accordingly, since no high repeatingstresses are exerted on the lead 11 during the temperature cycle afterthe wiring, the fatigue life is increased.

Further, during wiring operation at 1.5<α with an increased bendingstress ratio, since the bending ratio is concentrated only at theintermediate portion of the lead 11, a wiring state with a small radiusof curvature as shown in FIG. 80 is formed. Accordingly, since theinitial strength of the bent portion is lowered, the fatigue life duringthe temperature cycle after wiring is shortened.

As a result, an optimal wiring state with only a moderately distortedwiring shape is formed when the bending stress ratio is set within arange: 1.2≦α≦1.5 as in the Embodiment 1, and the temperature cycle lifeof the lead 11 can be increased.

The bending stress ratio α is defined as a value formed by dividing thestress σ1 generated at the end 49 of the lead 11 on the side of the tapeby a stress σ0 generated at the tape end 48 of the lead 11 uponconducting the operation of raising the lead 11 just above the bondingpad 7 with the bonding tool 18. That is, the bending stress ratio α canbe represented by the following formula based on the size of the lead 11having a feature in the tapered shape:α=σ1/σ0=b 1×(L 2−L 1)/(b 2×L 2)

As described above, when the size and the shape of the lead 11 aredesigned such that the bending stress ratio α is from 1.2 to 1.5, astable and suitable S-shaped wiring state can be formed by a simpledriving down movement of a wire bonder like that in the technique forthe planar S-shaped lead 26 described previously. Accordingly, since nospecial soft-modified wire bonder is required and the bonding tool trace25 can also be simplified, an effect of shortening the contact time uponbonding can also be expected.

12. Ni-Platingless Lead

To assist in providing a technical explanation of the Ni-platinglesslead, FIG. 54 is a cross sectional view illustrating a connectionportion of the lead, FIG. 55 is an enlarged cross sectional viewillustrating a bent portion of a lead, FIG. 56 is an enlarged crosssectional view illustrating a bent portion of an Ni-platingless lead,FIG. 57 is an enlarged cross sectional view illustrating a press contactportion of a lead and FIG. 58 is an enlarged cross sectional viewillustrating a press-contact portion of the Ni-platingless lead.

As an example, in the technique studied by the present inventor, in thecase of a cross sectional structure of a lead 11 in which Ni-plating isapplied to a surface of a Cu core and an Au plating is applied thereon,wherein a Cu core lead is employed instead of a pure Au lead, since theNi-plating layer is hard and brittle, if it is intended to produce anS-shaped lead configuration, there is the possibility of causing a crack51 to occur at the bent portion of the lead 11 as shown in FIG. 55, orthe bonding pad 7 or a portion therebelow may be subjected to damage 52as shown in FIG. 57. The Ni-plating is formed as a barrier layer forpreventing Cu atoms from diffusing to the Au plating surface.

On the contrary, in the Embodiment 1, since both the hardness and thebrittleness are reduced by using an Ni-platingless lead 11 in order toobtain the S-shaped configuration, the crack 51 is less likely to formthe lead per se and, in addition, the damage 52 to the semiconductorchip 1 at the counter-bonding face can also be moderated.

That is, in the connection state of the lead 11 as shown in FIG. 54, inthe lead having the constitution of a Cu core 53+Ni plating 54+Auplating 55, as shown in FIG. 55 as an enlargement of the portion A inFIG. 54, the crack 51 is liable to be caused as the radius of curvaturein the bent portion is smaller. On the other hand, if the surface of thelead 11 is free from the Ni plating 54 and, for example, is formed onlywith the Au plating 55 as shown in FIG. 56, the crack 51 is less likelyto form at the bent portion of the lead 11 even if the radius ofcurvature is identical with that in FIG. 55.

Further, also in a press-contact portion of the lead 11 in FIG. 57,illustrating an enlargement of the portion B in FIG. 54, the lead 11 hasa constitution comprising: Cu core 53+Ni plating 54+Au plating 55, andso damage 52 is liable to be caused at the periphery of a bonding pad 7.On the other hand, if the surface of the lead 11 is free from the Niplating 54 and, for example, is formed only with the Au plating 55 asshown in FIG. 58, the damage 52 is less likely even in a case of bondingunder the same lead bonding condition.

As described above, it is possible to suppress the occurrence of a crack51 in the lead 11 and moderate the damage 52 to the semiconductor chip 1while obtaining the S-shaped configuration, by constituting the lead 11such that only one plating layer, for example, an Au plating is formedon the core material of the Cu core 53.

Therefore, according to the semiconductor integrated circuit device inthe Embodiment 1, excellent effects can be obtained as already explainedby comparison with the package structure studied by the presentinventor, in the CSP package technique of substantially the identicalsize with that of the semiconductor chip, in each of the technicalitems, namely: 1. Surface wiring structure, 2. Optimization of the tapeedge position relative to the elastomer, 3. Optimization of outer sizeof the package, 4. Planar S-shaped lead, 5. Beam lead, 6. Peripheral PIQsize of bonding pad, 7. Improvement of anchor wiring, 8. Wide elastomerstructure, 9. Elastomer groove-fillage technique, 10. Inner lead bondingtechnique, 11. Lead design technique capable of forming S-shapedconfiguration with no tool return and 12. NI-platingless lead.

In the Embodiment 1, although various explanations have been made withreference to the drawings and the contents of various techniques on thepremise of a particular surface wiring structure, the technical items 2to 12 are not limited to the described surface wiring structure, but thetechnique of this invention is applicable also to general packagestructures, such as a rear face wiring structure. Accordingly, it can beexpected that the same effect as explained with reference to all of theitems can be obtained when the invention is applied to a general packagestructure.

The package structure of the Embodiment 1 (FIG. 1, FIG. 2) is shown fora case in which the elastomer 2 is larger than the outer shape of thesemiconductor chip 1. In a case where the elastomer 2 is smaller thanthe outer shape of the semiconductor chip 1, as shown in FIG. 81, animprovement of the moisture proofness or the like can be obtained byforming a package structure in which the lateral sides of thesemiconductor chip 1 and the elastomer 2 are covered with a sealant 6.

Embodiment 2

FIG. 59 and FIG. 60 are a cross sectional view and a perspective view,respectively, illustrating a rear face wiring solder resist structure inthe semiconductor integrated circuit device of Embodiment 2 according tothe present invention.

The semiconductor integrated circuit device of the Embodiment 2 is aball grid array type semiconductor package like that of the Embodiment1, but it is different from the Embodiment 1 in that it is not based onthe surface wiring technique, but is based on and provided for improvinga rear face wiring structure. For instance, as shown in FIG. 59 and FIG.60, in a structure comprising an elastomer 2 (elastic structuralmaterial) bonded on a main surface of a semiconductor chip (not shown)and a flexible wiring substrate 3 (wiring substrate) bonded to a mainsurface of the elastomer 2, a solder resist 56 (insulation film) isformed on the rear face of the flexible wiring substrate 3.

That is, the flexible wiring substrate 3 comprises a tape 9 (substratebase material) serving as a base material for the flexible wiringsubstrate 3 and wirings 10 bonded to the rear face of the tape 9, inwhich the rear face of the wiring 10 is bonded by way of the solderresist 56 to the elastomer 2. The solder resist 56 is composed of aninsulation material, such as a light sensitive epoxy resin like that inthe Embodiment 1.

The feature of the package structure of the semiconductor integratedcircuit device in the Embodiment 2 will be explained, including thestructure and the process of manufacture in comparison with a packagestructure employing a technique studied by the present inventor.

For instance, in the rear face wiring structure shown in FIG. 7, in theEmbodiment 1 as the technique studied by the present inventor, since theelastomer 2 is formed directly on the main surface of the wirings 10 ofthe flexible wiring substrate 3, low molecular weight ingredients of theelastomer 3 bleed directly to the lead 11 and if they bleed as far asthe bonding point of the lead 11, there is a likelihood of extremelydeteriorating the bondability (wire bonding stress) due to thecontamination.

Further, compared with the direct plating surface of the lead 11, thesurface of the tape 9 in which the wirings 10 are etched out between theleads 11 suffers from violent bleeding since the surface of the tape 9is roughened also with an aim of improving the bondability between thetape 9 and the wirings 10, and bleeding tends to be most violent at theedge portion of the lead 11 together with the effect of the surfacetension.

Further, in the rear face wiring structure in which the elastomer 2 isformed on an uneven surface of the wirings 10 caused by different levelsbetween the portions with or without the wirings 10, voids are liable tobe left, for example, in the gap between the wirings, which may cause adegrading of the reliability.

On the contrary, in the Embodiment 2, since the solder resist 56 isformed on the wirings 10 after forming the wirings 10 in themanufacturing step for the flexible wiring substrate 3, direct contactof the elastomer 2 with the wirings 10 can be prevented. In the samemanner, contact of the elastomer 2 to the roughened surface of the tape9 can also be prevented. This can suppress bleeding of the low molecularweight ingredients of the elastomer 2.

Further, by coating the solder resist 56 on the uneven surface of thewirings 10 of the flexible wiring substrate, the surface of the wirings10 is flattened to avoid a disadvantage, such as the creation of voidsupon forming the elastomer 2.

Accordingly, in the semiconductor integrated circuit device of theEmbodiment 2, since the solder resist 56 is formed on the wirings 10 ofthe flexible wiring substrate 3 in the CSP semiconductor packagetechnique based on the rear face wiring structure, it is possible toprevent the lowering of the bondability while preventing contaminationto the lead 11, thereby providing a package structure of highreliability with no voids.

Embodiment 3

FIG. 61 is a plan view of a semiconductor integrated circuit deviceforming an Embodiment 3 according to the present invention, as viewedfrom the rear face of a semiconductor chip, FIG. 62 is a plan viewthereof, FIG. 63 is a cross sectional view thereof, FIG. 64 is anenlarged cross sectional view of a portion A in FIG. 63 and FIG. 65 is aplan view for explaining the wiring structure of the wiring substrate.

A semiconductor integrated circuit device in the Embodiment 3 adopts,instead of a semiconductor package having a structure in which thebonding pad is formed approximately at the center of the chip, as in theEmbodiments 1 and 2 described above, a packaging structure using asemiconductor chip 1 a in which a pad is formed to the periphery of thechip, as shown in FIG. 61 to FIG. 65, and in which bumps 5 a connectedto the bonding pads to the semiconductor chip 1 a are disposed in aregion inward of the outer circumference of the semiconductor chip 1 a.The Embodiment 3 also has a structure which adopts the techniques from“1. Surface wiring structure” to “12. Ni-platingless lead” of Embodiment1, as well as the technical features of each of the technical items forthe rear face wiring solder resist structure as explained with referenceto the Embodiment 2.

That is, the semiconductor integrated circuit device in the Embodiment 3is, for example, a 24 pin ball grid array type semiconductor packagestructure, in which an elastomer 2 a (elastic structural material), aflexible wiring substrate 3 a (wiring substrate) having wirings 10 aformed on a tape 9 a and a solder resist 4 a (insulation film) aredisposed on a main surface of a semiconductor chip 1 a formed with aplurality of bonding pads 7 a (external terminals), solder bumps 5 a(bump electrodes) are formed to an opening of the solder resist 4 a, anda portion for forming the bonding pads 7 a and lateral sides of theelastomer 2 a and the flexible wiring substrate 3 a are covered with asealant 6 a.

The semiconductor chip 1 a has a peripheral pad structure, for example,as shown in FIG. 65, in which a plurality of bonding pads 7 a arearranged in a square pattern along the outer circumference of thesemiconductor chip 1 a. Each bonding pad 7 a of the semiconductor chip 1a is connected electrically with a solder bump 5 a by way of the wiring10 a of the flexible wiring substrate 3 a, which is connected at one endof the lead 11 a to the pad 7 a and joined at the bump land 12 a at theother end of the wiring 10 a to the bump 5 a. The solder bumps 5 a arearranged as a 6 row×4 column matrix in a region inward of thearrangement for the bonding pads 7 a.

Accordingly, in the semiconductor integrated circuit device of theEmbodiment 3, excellent effects can be obtained for each of thetechnical items as explained for the Embodiments 1 and 2, although thereis a difference in the semiconductor package structure relating to thefan-in peripheral pads. Particularly, in the fan-in package structure, aCSP structure package about the same size as the semiconductor chin 1 acan be attained similar to that in the Embodiments 1 and 2.

Embodiment 4

FIG. 66 is a plan view of a semiconductor integrated circuit deviceforming an Embodiment 4 of the present invention as viewed from the rearface of the semiconductor chip, FIG. 67 is a plan view thereof, FIG. 68is a cross sectional view thereof, FIG. 69 is an enlarged crosssectional view illustrating a portion A in FIG. 68 and FIG. 70 is a planview for explaining the wiring structure of a wiring substrate.

The semiconductor integrated circuit device of the Embodiment 4 adopts,instead of a semiconductor package having a structure in which the bumpelectrodes are disposed in the chip area as in the Embodiments 1 and 2,a package structure using a semiconductor chip 1 b of a peripheral padstructure as shown in FIG. 66 to FIG. 70, in which bumps 5 b connectedto the bonding pads of the semiconductor chip 1 b are disposed to aregion outward of the outer circumference of the semiconductor chip 1 b.This Embodiment 4 also has a structure for adopting the technique from“1. Surface wiring structure” to “12. Ni-platingless lead”, as explainedfor the Embodiment 1, as well as the features for each of the technicalitems of the rear face wiring solder resist structure explained for theEmbodiment 2, respectively.

That is, the semiconductor integrated circuit device of the Embodiment 4has, for example, a 80 pin ball grid array type semiconductor typepackage structure in which an elastomer 2 b (elastic structuralmaterial), a flexible wiring substrate 3 b (wiring substrate) havingwirings 10 b formed on a tape 9 b, and a solder resist 4 b (insulationfilm) are disposed on a main surface of a semiconductor chip 1 b formedwith a plurality of bonding pads 7 b (external terminals), solder bumps5 b (bump electrodes) are formed to an opening portion of the solderresist 4 b, portions for forming bonding pads 7 b are covered with thesealant 6 b, and a support ring 57 b is disposed to the lateral side ofthe semiconductor chip 1 b to constitute a package structure.

The semiconductor chip 1 b has a peripheral pad structure, for example,as shown in FIG. 70, and a plurality of bonding pads 7 b are arranged ina square pattern along the outer circumference of the semiconductor chip1 b. Each bonding pad 7 b of the semiconductor chip 1 b is connectedelectrically with a solder bump 5 b by way of the wiring 10 b of theflexible wiring substrate 3 b, which is connected at one end of the lead11 b with the pad 7 b and joined at the bump land 12 b at the other endwith the bump 5 b. The solder bumps 5 b are arranged in two rows in asquare pattern concentric to the arrangement of the bonding pads 7 b ofthe semiconductor chip 1 b.

Accordingly, the semiconductor integrated circuit device of theembodiment 4 can also provide excellent effects for each of thetechnical items as explained for the Embodiments 1 and 2, althoughhaving a different semiconductor package structure of fan-out peripheralpad configuration. Particularly, the fan-out package structure canprovide a package structure corresponding to multi-pin arrangements,although the size of the semiconductor package is increased comparedwith the Embodiments 1 and 2.

Embodiment 5

FIG. 71 is a plan view of a semiconductor integrated circuit deviceforming an Embodiment 5 of the present invention as viewed from the rearface of the semiconductor chip, FIG. 72 is a plan view thereof, FIG. 73is a cross sectional view thereof, FIG. 74 is an enlarged crosssectional view illustrating a portion A in FIG. 73 and FIG. 75 is a planview for explaining the wiring structure of a wiring substrate. In FIG.75, a portion, such as a number of the bonding pads and solder bumps, isomitted for simplification in order to make the arrangement of thewirings clearer.

The semiconductor integrated circuit device of the Embodiment 5 adopts,instead of a semiconductor package having a structure in which bumpelectrodes are disposed in the area of the chip as in the Embodiments 1and 2, a package structure using a peripheral pad structuresemiconductor chip 1 c as shown in FIG. 71 to FIG. 75, in which solderbumps 5 c connected to the bonding pads of the semiconductor chip 1 care disposed both in inner and outer regions of the semiconductor chip 1c. This Embodiment 5 also has a structure adopting the technique from“1. Surface wiring structure” to “12. Ni-platingless lead” as explainedfor the Embodiment 1, as well as features for each of the technicalitems of the rear face wiring solder resist structure, as explained forthe Embodiment 2.

That is, the semiconductor integrated circuit device in the Embodiment 5is, for example, a 110 pin ball grid array type semiconductor packagestructure in which an elastomer 2 c (elastic structural material), aflexible wiring substrate 3 c (wiring substrate) having wirings 10 cformed on a tape 9 c, and a solder resist 4 c (insulation film) on amain surface of a semiconductor chip 1 c formed with a plurality ofbonding pads 7 c (external terminals), solder bumps 5 c (bumpelectrodes) are formed to an opening portion of the solder resist 4 c, aportion of forming the bonding pads 7 c is covered with a sealant 6 cand a support ring 57 c is disposed to the lateral sides of thesemiconductor chip 1 c.

The semiconductor chip 1 c has a peripheral pad structure, for example,as shown in FIG. 75 (actual arrangement in FIG. 72) in which a pluralityof bonding pads 7 c are arranged in a square pattern along the outercircumference of the semiconductor chip 1 c. Each bonding pad 7 c of thesemiconductor chip 1 c is electrically connected to a solder bump 5 c byway of the wiring 10 c of the flexible wiring substrate 3 c that isconnected by a lead 1 c at one end to the pad 7 c and joined to the bump5 c at the bump land 12 c at the other end of the wiring 10 c. Thesolder bumps 5 c are arranged as 6 row×5 column array in a region inwardof the arrangement of the bonding pads 7 c of the semiconductor chip 1c, and are arranged in two rows in a square pattern also in the outerregion.

Accordingly, the semiconductor integrated circuit device of theEmbodiment 5 can also obtain the same excellent effect in each of thetechnical items as explained for the Embodiments 1 and 2, although thereis a difference in the semiconductor package structure. Particularly, inthe fan-in/out package structure, a package structure capable of copingwith multi-pin arrangements can be adopted, although the size of thesemiconductor package is enlarged compared with the Embodiments 1 and 2.

Embodiment 6

This embodiment is described in connection with FIGS. 82-94 and 108 ofthe drawings. A semiconductor device (CSP11′) according to the firstembodiment shown by FIG. 82 and FIG. 83 is a small structure whereof thepackage size is near the chip size. It comprises a semiconductor chip 1′having a main surface 1 a′ and an electrode pad (connection terminal orbonding pad) 1 b′ formed on the outer peripheral part of the mainsurface 1 a′, and bump electrodes 2′ which are external terminalsarranged on the inside of the semiconductor chip 1′. This structure,wherein a pad is formed on the periphery of the chip and bump electrodesare arranged inside the chip, will hereafter be referred to as aperipheral pad fan-in CSP.

As the external terminals are bump electrodes, the CSP11 is also a polegrid array.

Describing the structure of this CSP11′, it comprises an elastomer 3′(elastic structure) arranged on the main surface 1 a′ of thesemiconductor chip 1′ so as to leave electrode pads 1 b′ exposed, a thinfilm wiring substrate 4′ comprising a substrate main body 4 a′ providedwith wiring 4 d′ of which one end is electrically connected to theelectrode pads 1 b′ of the semiconductor chip 1′ via leads 4 c′ and theother ends are electrically connected to the bump electrodes 2′,openings 4 e′ for exposing the electrode pads 1 b′, and substrateprotruding parts 4 b′ which protrude beyond these openings 4 e′ and thesemiconductor chip 1′, and sealing parts 5′ which seal the electrodepads 1 b′ of the semiconductor chip 1′ and seal the leads 4 c′ of thethin film wiring substrate 4′, the substrate body 4 a′ and the substrateprotruding parts 4 b′ of the thin film wiring substrate 4′ being formedin a one-piece construction. (For the purpose of this invention,“wiring” shall be understood to mean parts formed on the tape, and“leads” shall be understood to mean parts protruding from the tapeincluding the wiring.)

The plan view of the CSP 11′ shown in FIG. 82 is a view through the sealpart 5′ shown in FIG. 83 in order to show the electrode pads 1 b′ of thesemiconductor chip 1′ and the leads 4 c′ of the thin film wiringsubstrate 4′.

Therefore, in the plan view of the CSP11′ shown in FIG. 82, theaforesaid sealing parts 5 are omitted, although the sealing parts 5′shown in FIG. 83 are actually formed in the openings 4 e′ of the thinfilm wiring substrate 4′ of the CSP11′ shown in FIG. 82 (this is alsothe case hereafter for Embodiments 7 to 25).

In this Embodiment 6, plural electrode pads 1 b′ (herein, six at oneside) are disposed on the periphery of each of the two short sides atright angles (hereinafter referred to as the short side direction) tothe longitudinal direction of the main surface 1 a′ of the rectangularsemiconductor chip 1′, and twelve bump electrodes 2′ which are externalterminals are therefore disposed in a grid shape covering a plan viewarea over the main surface of the semiconductor chip 1′.

Therefore, one each of the rectangular openings 4 e′ is formed at aposition corresponding to an outer edge facing the short side directionof the main surface of the semiconductor chip 1′ in the thin film wiringsubstrate 4′.

As a result, the plural electrode pads 1 b′ facing the short sidedirection of the semiconductor chip 1′ are exposed by the openings 4 e′of the thin film wiring substrate 4′ which are provided at correspondingpositions when the semiconductor chip 1′ is attached to the elastomer3′.

The thin film wiring substrate 4′ of the CSP 11′ according to the firstembodiment comprises a substrate body part 4 a′ comprising wiring 4 d′,two of the openings 4 e′, and substrate protruding parts 4 b′ whichprotrude beyond the substrate body 4 a′ and two openings 4 e′.

When the semiconductor chip 1′ is attached to the elastomer 3′, thesubstrate body 4 a′, elastomer 3′ and semiconductor chip 1′ arelaminated together, and the substrate protruding parts 4 b′ of the thinfilm wiring substrate 4′ then protrude in an anvil shape beyond thesemiconductor chip 1′.

Twelve bump lands 4 f′ (FIG. 89(a)) which are electrically connected tothe wiring 4 d′ and on which the bump electrodes 2′ are mounted, areprovided in the substrate body 4 a′.

The elastomer 3′ is an insulating elastic material which supports thesemiconductor chip 1′, and is arranged between the thin film wiringsubstrate 4′ and semiconductor chip 1′. The elastomer 3′ according tothe first embodiment comprises protruding parts 3 b′ (elastic protrudingparts) which protrude beyond the semiconductor chip 1′. After assemblingthe CSP11′, predetermined side faces 3 a′ of the elastomer 3′ (herein,the two side faces 3 a′ in the same direction as the longitudinaldirection of the semiconductor chip 1′) are exposed to the outside.

As shown in FIG. 82 or FIG. 83(c), when the elastomer 3′ is attached tothe thin film wiring substrate 4′, the elastomer protruding parts 3 b′which protrude beyond the semiconductor chip 1′ in the elastomer 3′ arelaid over the substrate protruding parts 4 b′ of the thin film wiringsubstrate 4′.

The sealing parts 5′ are formed by sealing the electrode pads 1 b′ ofthe semiconductor chip 1′ and the leads 4 c′ connected to them, thewhole of the opposite side faces 1 c′ in the short side direction of thesemiconductor chip 1′, and the area near both ends of the two oppositeside faces 1 c′ in the longitudinal direction of the semiconductor chip1′ with sealing resin. As the substrate protruding parts 4 b′ of thethin film wiring substrate 4′ are formed in the vicinity of thesemiconductor chip 1′, the sealing resin forms a bridge between(straddles) the substrate protruding parts 4 b′ and the semiconductorchip 1′ in the sealing parts 5′.

The specification of each part of the CSP11′ (materials, dimensions andthickness, etc.) will now be described referring to FIG. 84 (a, b, c,d). It should, however, be understood that these specifications are onlygiven as examples, and the invention is not to be construed as beinglimited in any way by them.

The tape which is the base material of the thin film wiring substrate 4′is formed of polyimide resin, and its thickness is of the order of 25 to75 μm. The wiring 4 d′ (comprising the leads 4 c′ and bump lands 4 f′)provided in the thin film wiring substrate 4′ is copper foil having athickness of the order of 18 to 25 μm. The wiring 4 d′ is plated with Auplating to a thickness of 1.5 μm on both sides, or Au/Ni plating ofdifferent thickness on the side of the electrode pad 1 b and the side ofthe bump electrode 2′.

In the thin film wiring substrate 4′ used in the sixth embodiment, thewiring 4 d′ is a single layer structure as shown in FIG. 83(a). It isalso “single layer back wiring” wherein the wiring 4D′ is formed only onthe under surface of the tape base material (tape base material 4 g′ inFIG. 87(a)).

The elastomer 3′ is a three-layer structure (FIG. 128) comprising a baselayer (skeleton layer 3 d′, referred to also as core layer) havingadhesive layers 3 e′ on both sides. Examples of its application arespecification (1) and specification (2) shown in FIG. 84 (a, b, c, d).Details of specification (1) are given in Japanese Patent ApplicationNo. Hei 9-149106 and details of specification (2) are given in JapanesePatent Application No. Hei 8-136159.

The elastomer 3′ used in the first embodiment is also colorless,therefore the elastomer 3′ according to the first embodiment is aneffectively transparent structure which transmits light.

From the viewpoints of porosity and water repelling properties, it isalso desirable that the base layer (skeleton layer 3 d′) of theelastomer 3′ is formed of a porous fluoride resin, i.e. it is desirableto use the elastomer of specification (1).

Herein, the elastomer 3′ formed from a porous fluoride resin comprises askeleton layer 3 d′ having a 3-dimensional mesh structure.

This 3-dimensional mesh structure is a non-woven fabric formed by3-dimensional entwining of a fibrous compound.

The sealing resin, which is the sealing material for forming the sealingparts 5, has the specification (1) or the specification (2) shown inFIG. 84 (a, b, c, d).

During cure bake after sealing, voids tend to form in the solvent typeliquid resin when the solvent vaporizes, and it is therefore desirableto use the resin of specification (1).

The sealing resin used in the CSP11′ of the first embodiment is amaterial of relatively high volatility. However, it is possible to usesealing resin of high volatility by increasing the displacement time ofa potting nozzle, not shown, during the coating step (e.g. approximately30 seconds for coating the six electrode pads 1 b′ on one side of thesemiconductor chip 1′), or by heating the sealing resin, and it is thuspossible to form a bridge of sealing resin between the substrateprotruding parts 4 b and semiconductor chip 1′.

It is also preferable to use a resin containing silica to reduceresidual stress due to contraction during seal cure, and more preferableto use a resin containing at least 50 weight percent silica.

The material of the bump electrode 2′ is Sn/Pb eutectic solder or otherhigh melting point solder, or Au-plated Ni or the like, and its diameteris of the order of 0.3-0.6 mm.

The CSP11′ (semiconductor device) of the first embodiment offers thefollowing advantages.

The substrate body 4 a′ and substrate protruding parts 4 b′ of the thinfilm wiring substrate 4′ are formed in a one-piece construction. As thesubstrate protruding parts 4 b′ are not a separate structure from thesubstrate body 4 a′, it is not necessary to form the substrateprotruding parts 4 b′ from costly materials.

Therefore, the cost of manufacturing the CSP11′ (semiconductor device)is reduced.

As the substrate protruding parts 4 b′ protrude beyond the openings 4 e′in the thin film wiring substrate 4′, the sealing parts 5′ may be formedas a bridge between the substrate protruding parts 4 b′ and thesemiconductor chip 1′ when the sealing resin is applied via the openings4 e′.

As a stable seal is obtained sealing properties are improved and, as aresult, humidity resistance is more reliable.

The sealing resin contains at least 50 weight percent silica, soresidual stress due to contraction in cure bake can be reduced.Therefore, the reliability of the sealing parts 5 is improved.

The base layer of the elastomer 3′ which forms the elastic structure isconstructed of a porous fluoride resin, and the two opposite side faces3 a of the elastomer 3′ in the same direction as the longitudinaldirection of the semiconductor chip 1′ are exposed to the outside.Therefore, water vapor due to moisture absorbed during reflow can bereleased to the outside, reflow properties are improved, and entry ofwater into the CSP11′ can be prevented by the water repelling propertiesof the fluoride in the porous fluoride resin. As a result, degradationof electrical properties of the CSP11′ is reduced.

Next, the method of manufacturing the CSP11′ (semiconductor device) ofthe first embodiment will be described together with the advantagesgained therefrom.

The method will be described in the sequence shown in FIG. 104 referringto the process conditions shown in FIG. 5.

The elastomer 3′ shown in FIG. 90, FIG. 91, FIG. 93 and FIG. 94comprises openings 3 c. These figures describe the method ofmanufacturing the CSP16′, 17′ of the Embodiments 11 or 12 to bedescribed later, but since the Embodiment 6 is the same as regards thebasic manufacturing method, FIG. 90, FIG. 91, FIG. 93 and FIG. 94 willbe used also in the Embodiment 6.

First, the thin film wiring substrate 4′ comprising the substrate body 4a′ comprising the wiring 4 d′, and the substrate protruding parts 4 b′which protrude beyond the openings 4 e′ in which the leads 4 c′ areconnected to the wiring 4 d′, is provided.

The method of manufacturing the thin film wiring substrate 4′ will bedescribed referring to FIG. 87 to FIG. 89.

First, the tape base material 4 g′ comprising the polyimide resin shownin FIG. 87(a) is prepared. An adhesive for attaching the copper foil 4h′ shown in FIG. 88(b) is coated on the top and under surfaces of thisbase tape 4 g′.

Next, preparing holes 4 i′ for tape feed are formed at an approximatelyequal interval on both sides of the tape base material 4 g′ as shown inFIG. 87(b).

Next, twelve bump openings 4 j′ and two wiring join holes 4 e′ on bothsides are formed by stamping as shown in FIG. 88(a) and the copper foil4 h′ is laminated on the tape base material 4 g′ as shown in FIG. 88(b).

The copper foil 4 h′ is then fashioned into a desired pattern by etchingas shown in FIG. 89(a) so as to form a wiring pattern.

This forms the bump lands 4 f′ and a power supply line 4 k′.

In order to make the aforesaid gold plating electrically react afterplating the copper foil 4 h′, adjacent power supply lines 4 k′ must beconnected together.

After etching the copper foil 4 h′ to form the wiring pattern, thecopper foil 4 h′ is gold plated. The specification of this gold platingis that of the wiring plating shown in FIG. 84 (a, b, c, d). It may begold plating having a thickness of 1.5 μm (wiring plating (1) shown inFIG. 84 (a, b, c, d)), gold/nickel differential thickness plating(wiring plating (2) shown in FIG. 84 (a, b, c, d)), or another type ofplating.

The wiring leads which are connected together as shown in FIG. 89(a) arethen cut by a punch die 6 a′ of a cutter 6′ shown in FIG. 92(a) so as toseparate the leads 4 c′ as shown in FIG. 89(b).

As regards the width of the cutting blade of the punch die 6′, it isdesirable to use a small cutting blade having a width of the order of 50to 200 μm and more preferably 100 to 150 μm so that the leads 4 c′ canbe fashioned into a beam shape 41′ after cutting as shown in FIG. 92(b).

By using a small cutting blade of the order of 125 μm, the cut parts ofthe leads 4 c′ can be formed with a dimension of the order of 125 μm,and as a result, the distance between the semiconductor chip 1′ and thesubstrate protruding parts 4 b′ can be shortened when the semiconductorchip 1 (FIG. 82) is mounted.

The sealing areas of the sealing parts 105 can therefore be made narrow,so sealing properties are improved.

Also as the distance between the semiconductor chip 1′ and the substrateprotruding parts 4 b′ can be made short, the CSP 11′ can be madecompact.

By cutting so as to fashion the leads 4 c′ into the beam shape 41′ shownin FIG. 92(b), the thin film wiring substrate 4′ shown in FIG. 89(b) isproduced.

The detailed structure of the thin film wiring substrate 4′ used in thesixth embodiment will now be described referring to FIG. 89 and FIG.108.

As shown in FIG. 108, four long holes 4 q′ effectively corresponding tothe four sides of the substrate body 4 a′ are formed around thesubstrate body 4 a′.

The purpose of these holes 4 q′ is to reduce the cross-sectional areawhen the substrate body 4 a′ is cut off, improve ease of cutting, and tolessen distortion when winding up or cutting the thin film wiringsubstrate 4′ which is in the form of a long thin tape.

Positioning holes 4 p′ for positioning during cutting are providedoutside the upper and lower long holes 4 q′ of the substrate body 4 a′(according to this embodiment a total of three holes is provided, i.e.one upper one and two lower ones), but there is no limit on the numberof these positioning holes 4 p′ if they are provided outside both theupper and lower long holes 4 q′.

Recognition patterns 4 n′ formed of the same copper foil as the wiringpattern are also provided in these upper and lower long holes 4 q′ ofthe substrate body 4 a′.

These recognition patterns 4 n′ are used to recognize the position ofthe thin film wiring substrate 4′ during cutting, etc., and are suchthat they can be recognized also from the reverse side of the thin filmwiring substrate 4′ (side on which there is no wiring pattern) duringbonding. Specifically, they straddle the ends of the long holes 4 q′ sothat they can be recognized from the top surface and under surface ofthe thin film wiring substrate 4′.

The thin film wiring substrate 4′ shown in FIG. 108 comprises pluralsubstrate bodies 4 a′ arranged horizontally in a row with respect to thefeed direction, however plural rows of the substrate bodies 4 a′ (e.g.two) may be arranged horizontally.

In this case, the efficiency of manufacturing the CPU11 may be improved.

Subsequently, thin film wiring substrate supply 20′ and elastomer supply21′ shown in FIG. 85 are performed, and elastomer attachment 22′ isperformed.

To attach the elastomer 3′, the substrate body 4 a′ of the thin filmwiring substrate 4′ and elastomer 3′ are joined as shown in FIG. 90(a)based on elastomer attachment conditions whereof an example is given inFIG. 86. In this way, the thin film wiring substrate 4 is assembled withthe elastomer 3′. When the elastomer 3′ is attached, there may be threepositional relationships of the elastomer 3′ and substrate body 4 a′ asshown in FIGS. 93(a), 93(b), 93(c).

First, FIG. 93(a) shows the case where the edge of the substrate body 4a′ protrudes beyond the elastomer 3′ by an protruding amount P.

FIG. 93(b) shows the case where the edge of the substrate body 4 a′ andthe edge of the elastomer are perfectly aligned. FIG. 93(c) shows thecase where the edge of the substrate body 4 a′ falls short of theelastomer 3′ by an amount Q.

In general, during heat curing after applying a sealing material(herein, a sealing resin), volatile components of the sealing materialare produced as volatile gases. As the specific gravity of thesevolatile gases is less than that of the sealing material, the volatilegases escape to the outside from the upper part of the sealing material.

However, when a P value predetermined range described hereafter isexceeded and the edge of the elastomer 3′ does not protrude to the edgeof the substrate body 4 a′ (P>300 μm), volatile gases produced furtherinside than the edge of the substrate body 4 a′ cannot escape to theoutside of the sealing material as the upper part is obstructed by theedge of the substrate body 4 a′, so these gases remain as bubbles in thesealing material.

After heat curing of the sealing material, part of the components of thevolatile gases in the bubbles gradually escape to the outside throughminute (intermolecular) gaps in the sealing material, so the internalpressure of the bubbles is released.

As a result, voids are formed in the sealing material where the bubblesoccur.

The voids create unfilled spaces in areas which should be filled bysealing material, and have an adverse effect on the humidity resistanceand temperature cycle reliability of the semiconductor device.

It is therefore desirable that the value of P lies within a P valuepredetermined range of O≦P≦300 μm, and preferably O≦P≦100 μm, so thatthe escape path of the volatile gases is not obstructed by the substratebody 4 a′, and so that the volatile gases produced can be releasedoutside the sealing material.

If this is done, voids are not formed in the sealing material.

On the other hand, when a Q value predetermined range describedhereafter is exceeded and the edge of the elastomer 3′ protrudes beyondthe edge of the substrate body 4 a′ (Q>100 μm), part of the leads 4 c′is fixed by the elastomer 3′, so a correct wiring configuration cannotbe formed when the leads 4 c′ are bonded.

This has an adverse effect on temperature cycle reliability.

It is therefore desirable that the position of the edge of the elastomer3′ relative to the edge of the substrate body 4 a′ is within a Q valuepredetermined range of for example 0≦Q≦100 μm, and preferably 0≦Q≦50 μm,so that correct bonding of the leads 4 c′ can be performed.

Hence, by ensuring that P and Q are within the predetermined ranges, aCSP11′ of high reliability can be manufactured free of voids in thesealing material and wherein the leads 4 c′ are correctly bonded.

Subsequently, chip supply 23′ (FIG. 85) is performed wherein thesemiconductor chip 1′ is supplied having the electrode pads 1 b′ on theouter periphery of the main surface 1 a′ as shown in FIG. 83(a). Chipattachment 24′ shown in FIG. 85 is then performed based on the chipattachment conditions shown in FIG. 86.

Herein, in the chip attachment 24′, the main surface 1 a′ of thesemiconductor chip 1′ is joined to the elastomer 3′ as shown in FIG.83(a) leaving the electrode pads 1 b′ of the semiconductor chip 1′exposed in the openings 4 e′ of the thin film wiring substrate 4′, asshown in FIG. 82.

Specifically, the semiconductor chip 1′ is attached to the top of theelastomer 3′ as shown in FIG. 90(b).

Subsequently, an elastomer cure bake 25′ shown in FIG. 85 is performedbased on the post-chip attachment cure conditions shown in FIG. 86 so asto raise the joining strength of the elastomer 3′ and semiconductor chip1′.

Next, inner lead connections 26′ shown in FIG. 85 is performed based onthe inner lead connection conditions shown in FIG. 86. Two sets of innerlead connection conditions (1) and (2) are shown in FIG. 86, however theinner lead connection conditions are not limited to this.

First, a bonding tool 7′ is lowered to a predetermined position as shownin FIG. 94(a), then one of the leads 4 c′ of the thin film wiringsubstrate 4′ is pressed onto the corresponding electrode pad 1 b′ on thesemiconductor chip 1′ by the bonding tool 7′ so that the lead 4 c′ andthe electrode pad 1 b′ are electrically connected.

The bonding method of the first embodiment is single bonding.

After bonding, the lead 4 c′ is pushed up by the bonding tool 7′ so thatit is just above the electrode pad 1 b′. If a value obtained by dividingthe stress produced in the taper-shaped tip of the lead 4 c′ by thestress produced at the edge of the substrate body 4 a′ is defined as abending stress ratio alpha, this bending stress ratio α is given by thefollowing expression from the dimensions of the taper-shaped lead 4 c′:(α=:L×(K−J)/(M×K)(FIG. 94(a)).

The dimensions and shape of the lead 4 c′ are therefore designed suchthat the bending stress ratio α is within the range 1.0 to 1.75.

Subsequently, supply of sealing resin which is the sealing material,i.e. a sealing material supply 27′, is performed as shown in FIG. 85.

Specifically, a resin sealing 28 shown in FIG. 85 is performed using asealing material (sealing resin) shown in the sealing materialspecifications of FIG. 83(a, b, c, d).

In this step, the sealing resin is allowed to drip from the opening 4 e′of the thin film wiring substrate 4′ shown in FIG. 82 by a pottingmethod using a potting nozzle, not shown, and the electrode pad 1 b′ ofthe semiconductor chip 1′ and lead 4 c′ of the thin film wiringsubstrate 4 are sealed so as to form the sealing parts 5′. The drip timemay be for example 30 seconds for the openings 4 e′ on one side.

As the space between the substrate protruding parts 4 b′ andsemiconductor chip 1′ can be sealed in a bridge-like fashion in the CSP11′ of the first embodiment, a stable resin sealing 28′ can beperformed, and the humidity resistance of the sealing parts 5′ cantherefore be made more reliable.

Next, a sealing material cure bake step 29′ shown in FIG. 85 isperformed based on the post-seal curing conditions shown in FIG. 86 soas to harden the sealing parts 5′.

Also, a pole supply 30′ (FIG. 85) is performed for supplying a bump polematerial shown in the bump pole specifications of FIG. 84 (a, b, c, d)to the bump openings 4 j′ (FIG. 88(a)).

A bump forming 31′ shown in FIG. 85 is then performed based on thereflow conditions for bump forming shown in FIG. 86.

The bump forming 31′ is performed by passing the material obtained bysupplying the pole material to the openings 4 j′ of the substrate body 4a′ through a reflow furnace, not shown.

This electrically connects the wiring 4 d′ to the bump electrodes 2′ asshown in FIG. 82 and FIG. 83.

When the bump electrodes 2′ are formed according to the firstembodiment, even if the CSP11′ has absorbed moisture and is passedthrough reflow, the side faces 3 a′ in a predetermined direction of theelastomer 3′ (herein, the two opposite side faces 3 a′ in the samedirection as the longitudinal direction of the semiconductor chip 1′)are exposed to the outside, so water vapor produced during reflow candisperse to the outside through the elastomer 3′. Reflow tolerance istherefore improved.

Next, a mark 32′ (FIG. 85) for marking a number of the product (CSP11′)is performed.

Subsequently, a cutting 33′ shown in FIG. 85 is performed at a cuttingposition 8′ shown in FIG. 91 so as to obtain different CSP11′ of desiredsizes.

Embodiment 7

FIG. 95 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a seventh embodiment ofthis invention. FIGS. 96(a) to 96(c) are diagrams showing the structureof the semiconductor device shown in FIG. 95. FIG. 96(a) is across-sectional view through a line 96A-96A in FIG. 95, FIG. 96(b) is across-sectional view through a line 96B-96B in FIG. 95, FIG. 96(c) is across-sectional view through a line 96C-96C in FIG. 95.

A CSP12′ (semiconductor device) according to the second embodiment is aperipheral pad fan-in CSP as is the CSP11′ of the sixth embodiment shownin FIG. 82. It has a substantially identical structure to that of theCSP11′; however, a difference from the CSP11′ of the sixth embodiment isthat in the cutting step 33′ after the bump forming 31′ shown in FIG.85, in the regions of the sealing parts 5′ formed in the protruding part4 b′, the substrate protruding parts 4 b′ and the sealing parts 5′ aresimultaneously cut to a desired size. In this way, the CSP12′ can bemade even more compact than the CSP11′ shown in FIG. 82.

To implement this, a low silica sealing resin having a low proportion ofsilica must be used as sealing resin.

Specifically, the proportion of silica (filler) in the sealing resinmust lie within the range of 0 to 50 weight percent, and it ispreferably 0 weight percent.

The silica mentioned herein is extremely hard, but it lowers theresidual stress of the sealing resin in the sealing material cure bakeshown in FIG. 85.

The remaining features of the construction of the CSP12′ according tothe second embodiment and of its method of manufacture are identical tothose of the CSP11′ of the first embodiment, so their description willnot be repeated.

The advantages of the CSP12′ of the second embodiment and its method ofmanufacture are as follows.

First, in the region of the sealing parts 5′ formed in the substrateprotruding parts 4 b′, the substrate protruding parts 4 b′ and sealingparts 5′ are simultaneously cut to a desired size. As this cutting isperformed regardless of the extent to which sealing resin has spread inthe substrate protruding parts 4 b′ (size of the sealing parts 5′ formedin the substrate protruding parts 4 b′), the CSP12′ can be made compact.

As the proportion of silica in the sealing resin is low, the hardness ofthe sealing parts 5′ after the sealing resin has hardened can belowered, so the life of the cutting die used to cut the substrateprotruding parts 4 b′ and sealing parts 5′ can be lengthened.

The remaining advantages of the CSP12′ according to the secondembodiment and of its method of manufacture are identical to those ofthe CSP11′ of the first embodiment, so their description will not berepeated.

Embodiment 8

FIG. 97 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to an eighth embodiment ofthis invention. FIGS. 98(a) to 98(c) are diagrams showing the structureof the semiconductor device shown in FIG. 97. FIG. 98(a) is across-sectional view through a line 98A-98A in FIG. 97, FIG. 98(b) is across-sectional view through a line 98B-98B in FIG. 97, FIG. 98(c) is across-sectional view through a line 98C-98C in FIG. 97.

A CSP13′ (semiconductor device) according to Embodiment 8 is aperipheral pad fan-in CSP as is the CSP12′ of the Embodiment 7 shown inFIG. 95 and FIG. 96. It has a substantially identical structure to thatof the CSP12′; however, a difference from the CSP12′ of the secondembodiment is that in the resin sealing step 28′ shown in FIG. 85, theresin sealing 28′ is performed on the two opposite side faces 1 c′ inthe longitudinal direction of the semiconductor chip 1′ as shown in FIG.98(c) as well as the resin sealing 28′ of Embodiment 6.

During the resin sealing 28′ performed on the two opposite side faces 1c′ in the longitudinal direction of the semiconductor chip 1′, after thesealing material cure bake 29′ of the sixth embodiment, the CSP13′ istemporarily turned over with its top surface and under sides reversed.

Sealing resin is then applied again to the two opposite side faces 1 c′in the longitudinal direction of the semiconductor chip 1′ and theadjacent substrate protruding parts 4 b′ from the under surface (reverseside to the main face 1 a) of the semiconductor chip 1′ so as to repeatthe resin sealing 28′.

Subsequently, in the cutting step 33′ shown in FIG. 85, the substrateprotruding parts 4 b′, elastomer protruding parts 3 b′ of the elastomer3′ and the sealing parts 5′ formed therein are simultaneously cut to thedesired size.

As a result, in the CSP13′ of the third embodiment, the resin sealing28′ is performed over all the four side faces 1 c of the semiconductorchip 1′ as shown in FIG. 98, and the sealing parts 5′ are thereby formedon all the four side faces 1 c′ of the semiconductor chip 1′.

The remaining features of the construction of the CSP13′ according tothe eighth embodiment and of its method of manufacture are identical tothose of the CSP12′ of the first embodiment, so their description willnot be repeated.

The advantages of the CSP13′ of the eighth embodiment and its method ofmanufacture are as follows.

In the CSP13′, all of the four side faces 1 c′ of the semiconductor chip1′ are covered by sealing resin, so the seal properties (herein,humidity resistance) of the semiconductor chip 1′ are improved.

As a result, a compact, highly reliable CSP13′ can be obtained.

The remaining advantages of the CSP13′ according to the eighthembodiment and of its method of manufacture are identical to those ofthe CSP12′ of the seventh embodiment, so their description will not berepeated.

Embodiment 9

FIG. 99 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a third embodiment of thisinvention. FIGS. 100(a) to 100(c) are diagrams showing the structure ofthe semiconductor device shown in FIG. 99. FIG. 100(a) is across-sectional view through a line 100A-100A in FIG. 99, FIG. 100(b) isa cross-sectional view through a line 10B-10B in FIG. 99, FIG. 100(c) isa cross-sectional view through a line 100C-100C in FIG. 99.

A CSP14′ (semiconductor device) according to the ninth embodiment is aperipheral pad fan-in CSP as is the CSP13′ of the eighth embodimentshown in FIG. 97 and FIG. 98. It has a substantially identical structureto that of the CSP13′, however a difference from the CSP13′ of the thirdembodiment is that the elastomer 3′ and the substrate body 4 a′ of thethin film wiring substrate 4′ are formed with substantially the samesize, as shown in FIG. 98.

In other words, the elastomer 3′ in the CSP14′ of the ninth embodimentdoes not comprise the elastomer protruding parts 3 b′ shown in the sixthto eighth embodiments.

Therefore, when the resin sealing 28′ is performed by the same method asthe resin sealing 28′ of the eighth embodiment, all of the four sidefaces 3 a′ of the elastomer 3′ are covered by sealing resin as well asthe all of the four side faces 1 c′ of the semiconductor chip 1′.

Consequently, all of the outer side faces 1 c′, 3 a′ of thesemiconductor chip 1′ and elastomer 3′ are covered together to form thesealing parts 5′, and the sealing parts 5′ covering all of the outerside faces 1 c′, 3 a′ are also directly joined to the substrateprotruding parts 4 b′ of the thin film wiring substrate 4′.

Moreover, all of the surfaces of the elastomer 3′ are covered by thesealing parts 5′, substrate body 4 a′ and semiconductor chip 1′.

The remaining features of the construction of the CSP14′ according tothe ninth embodiment and of its method of manufacture are identical tothose of the CSP13′ of the eighth embodiment, so their description willnot be repeated.

The advantages of the CSP14′ of the ninth embodiment and its method ofmanufacture are as follows.

In the CSP14′, as all of the surfaces of the elastomer 3′ are covered,the same advantages as when the side faces 3 a′ of the elastomer 3′ areexposed cannot be obtained. However as all of the side faces 1 c′, 3 a′of the semiconductor chip 1 and elastomer 3′ are covered so as to formthe sealing parts 5′, and all of the peripheral sealing parts 5′ aredirectly joined to the substrate protruding parts 4 b′ of the thin filmwiring substrate 4′, the seal properties (humidity resistance) of thesemiconductor chip 1′ are further improved.

The remaining advantages of the CSP14′ according to the fourthembodiment and of its method of manufacture are identical to those ofthe CSP13′ of the eighth embodiment, so their description will not berepeated.

Embodiment 10

FIG. 101 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a tenth embodiment of thisinvention. FIGS. 102(a) to 102(c) are diagrams showing the structure ofthe semiconductor device shown in FIG. 101. FIG. 102(a) is across-sectional view through a line 102A-102A in FIG. 101, FIG. 102(b)is a cross-sectional view through a line 102B-102B in FIG. 101, FIG.102(c) is a cross-sectional view through a line 102C-102C in FIG. 101.

A CSP15′ (semiconductor device) according to the tenth embodiment is aperipheral pad fan-in CSP as is the CSP14′ of the fourth embodimentshown in FIG. 99 and FIG. 100. It has a substantially identicalstructure to that of the CSP14′; however, a difference from the CSP14′of the fourth embodiment is that seal openings 4 m′ are provided atpositions corresponding to the two opposite side faces 1 c′ in thelongitudinal direction of the semiconductor chip 1′ (FIG. 102(c)) in thesubstrate protruding parts 4 b′ of the thin film wiring substrate 4′ inaddition to the openings 4 e′ exposing the electrode pads 1 b′, as shownin FIG. 101.

Specifically, the two openings 4 e′ are provided at positions exposingthe electrode pads 1 b on both sides of the semiconductor chip 1′, andthe two opposite seal openings 4 m′ are provided in a direction at rightangles to them, in the thin film wiring substrate 4′ of the CSP14′according to the ninth embodiment.

Hence, when the resin sealing 28′ shown in FIG. 85 is performed, sealingresin can be applied through the openings 4 e′ and the seal openings 4m′ from the top surface of the thin film wiring substrate 4′.

Therefore, the four side faces 1 c′ of the semiconductor chip 1′ can becovered by sealing resin by this bonding method.

The remaining features of the construction of the CSP15′ according tothe tenth embodiment and of its method of manufacture are identical tothose of the CSP14′ of the ninth embodiment, so their description willnot be repeated.

The advantages of the CSP15′ of the tenth embodiment and of its methodof manufacture are as follows.

In the CSP15′, as the resin sealing 28′ is performed by applying sealingresin through the openings 4 e′ and the seal openings 4 m′ from the topsurface (one side) of the thin film wiring substrate 4′, there is noneed to turn the CSP15′ over during the resin sealing step, soproductivity is improved.

The remaining advantages of the CSP14′ according to the tenth embodimentand of its method of manufacture are identical to those of the CSP13′ ofthe ninth embodiment, so their description will not be repeated.

Embodiment 11

FIG. 103 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to an eleventh embodiment ofthis invention. FIGS. 104(a) to 104(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 103. FIG. 104(a) isa cross-sectional view through a line 104A-104A in FIG. 103, FIG. 104(b)is a cross-sectional view through a line 104B-104B in FIG. 103, FIG.104(c) is a cross-sectional view through a line 104C-104C in FIG. 103.

A CSP16′ (semiconductor device) according to the eleventh embodiment isa peripheral pad fan-in CSP as is the CSP12′ of the seventh embodimentshown in FIG. 95 and FIG. 96. It has a substantially identical structureto that of the CSP12′, however a difference from the CSP12′ of theseventh embodiment is that openings 3 c′ to those in the thin filmwiring substrate 4′ are provided also in the elastomer 3′ to expose theelectrode pads 1 b′ of the semiconductor chip 1′, as shown in FIG. 103.

Specifically, the elastomer 3′ in the CSP16′ comprises the two openings3 c′ exposing the electrode pads 1 b′, and elastomer protruding parts 3b′ (elastic structure protruding parts) which protrude beyond theseopenings 3 c′ and the semiconductor chip 1′.

Hence, when the elastomer 3′ is attached to the thin film wiringsubstrate 4′, the positions of the two openings 4 e′ and 3 c′ in thesemembers can be aligned.

The elastomer protruding parts 3 b′ of the eleventh embodiment areprovided around the whole periphery of the elastomer 3′.

The resin sealing 28′ (FIG. 85) in the CSP16′ according to the eleventhembodiment is identical to the resin sealing 28′ according to theseventh embodiment.

The elastomer protruding parts 3 b′ which are provided in the elastomer3′ beyond the openings 3 c′ have the additional effect of a dampreventing flow of sealing resin.

Therefore in the CSP16′ according to the eleventh embodiment, thesubstrate protruding parts 4 b′ of the thin film wiring substrate 4′ andthe elastomer protruding parts 3 b′ laminated on them may besimultaneously cut in the cutting step 33′ shown in FIG. 85, so the chippackage may be made compact.

Specifically, the contour of the thin film wiring substrate 4′ andelastomer 3′ are cut to effectively the same size in the cutting step33′.

Further in the CSP16′, as the sealing parts 5′ formed by the resinsealing 28′ are not cut in the cutting step 33′, a sealing resincomprising 50 weight percent or more of silica may be used.

The remaining features of the construction of the CSP16′ according tothe eleventh embodiment and of its method of manufacture are identicalto those of the CSP12′ of the seventh embodiment, so their descriptionwill not be repeated.

The advantages of the CSP16′ of the eleventh embodiment and its methodof manufacture are as follows.

In the CSP16′, leakage of sealing resin during the resin sealing step28′ is prevented by the elastomer protruding parts 3 b′ provided in theelastomer 3′.

As the elastomer protruding parts 3 b′ are provided around the wholeperiphery of the elastomer 3′, leakage of sealing resin may be preventedover the whole of the substrate protruding parts 4 b′ of the thin filmwiring substrate 4′.

There is therefore no need to cut the sealing resin in the cutting step33′, and the contour of the CSP16′ may be made compact.

Further as sealing resin is not cut in the cutting step 33′, a sealingresin comprising 50 weight percent or more of silica may be used.

The contraction factor of the sealing resin in the resin material curebake step 29′ shown in FIG. 85 is thereby reduced, and residual stressin the sealing resin is reduced.

The remaining advantages of the CSP16′ according to the eleventhembodiment and of its method of manufacture are identical to those ofthe CSP12′ of the seventh embodiment, so their description will not berepeated.

Embodiment 12

FIG. 105 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a twelfth embodiment ofthis invention. FIGS. 106(a) to 106(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 105. FIG. 106(a) isa cross-sectional view through a line 106A-106A in FIG. 105, FIG. 106(b)is a cross-sectional view through a line 106B-106B in FIG. 105, FIG.106(c) is a cross-sectional view through a line 106C-106C in FIG. 105.

A CSP17′ (semiconductor device) according to the twelfth embodiment is aperipheral pad fan-in CSP as is the CSP16′ of the eleventh embodimentshown in FIG. 103 and FIG. 104. It has a substantially identicalstructure to that of the CSP16′; however, a difference from the CSP16′of the eleventh embodiment is that the elastomer 3′ is made sufficientlythick when the CSP17′ is assembled that the four side walls 1 c′ of thesemiconductor chip 1′ are surrounded by the elastomer protruding parts 3c′ of the elastomer 3′, as shown in FIGS. 106(a), 106(b), 106(c).

In the CSP17, as the elastomer 3′ is made thick, the elastomer 3′ can beformed of a porous fluoride resin.

Therefore, in the CSP17′ according to the seventh embodiment, thesemiconductor chip 1′ is attached so that the peripheral side faces 1 c′are surrounded only by the elastomer protruding parts 3 b′ (elasticstructure protruding parts) of the elastomer 3′, as shown in FIG.106(c).

FIG. 107 shows the layout of the wiring 4 d′ in the CSP17′.

The method of attaching (fixing) the semiconductor chip 1′ shown in FIG.106(c) will now be described.

To perform the chip attachment 24′ shown in FIG. 85, the semiconductorchip 1′ is pushed into the elastomer 3′ by making use of the fact thatthe elastomer 3′ is a porous fluoride resin.

As the elastomer 3′ is a porous fluoride resin, it can be easilydepressed under a comparatively small load.

The thickness of the elastomer 3′ directly underneath the semiconductorchip 1′ can therefore be made much smaller than the thickness of theouter periphery of the semiconductor chip 1′.

As a result, the semiconductor chip 1′ can be formed into a structurewherein the side faces 1 c′ on the outer periphery are surrounded by theelastomer protruding parts 3 b′ formed all around the periphery.

Sealing resin is then applied through the openings 4 e′ of the thin filmwiring substrate 4′ and the openings 3 c′ of the elastomer 3′ so as toform the sealing parts 5′ at both ends of the semiconductor chip 1′.

Therefore in the CSP17′, by pressing the semiconductor chip 1′ into theelastomer 3′, the region near the center of the opposite side faces 1 c′in the longitudinal direction of the semiconductor chip 1′ is covered bythe elastomer protruding parts 3 b′ of the elastomer 3′ without sealingusing sealing resin, as shown in FIG. 106(c).

The remaining features of the construction of the CSP17′ according tothe twelfth embodiment and of its method of manufacture are identical tothose of the CSP16′ of the eleventh embodiment, so their descriptionwill not be repeated.

The advantages of the CSP17′ of the seventh embodiment and its method ofmanufacture are as follows.

In the CSP17′, as the elastomer 3′ is a porous fluoride resin, and asthe thickness of the elastomer 3′ directly underneath the semiconductorchip 1′ can be made much smaller than that of the outer periphery of thesemiconductor chip 1′, the semiconductor chip 1′ can be attached so thatthe side faces 1 c′ on the outer periphery of the semiconductor chip 1′are surrounded by the elastomer protruding parts 3 b′.

Hence, flow of sealing resin to the outside during the resin sealingstep 28′ of FIG. 85 is prevented by the elastomer protruding parts 3 b′and it is unnecessary to cut the sealing resin, so the CSP17′ may bemade compact.

The remaining advantages of the CSP17′ according to the seventhembodiment and its method of manufacture are identical to those of theCSP16′ of the eleventh embodiment, so their description will not berepeated.

Embodiment 13

FIG. 109 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a thirteenth embodiment ofthis invention. FIGS. 110(a) to 110(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 109. FIG. 110(a) isa cross-sectional view through a line 110A-110A in FIG. 109, FIG. 110(b)is a cross-sectional view through a line 110B-110B in FIG. 109, FIG.110(c) is a cross sectional view through a line 110C-110C in FIG. 109.

A CSP18′ (semiconductor device) according to the thirteenth embodimentis a peripheral pad fan-in CSP as is the CSP12′ of the seventhembodiment shown in FIG. 95. It has a substantially identical structureto that of the CSP12′; however, a difference from the CSP12′ of thesecond embodiment is that open rectangular dam pieces 34′ are providedaround the openings 4 e′ on the surfaces of the substrate protrudingparts 4 b′ of the thin film wiring substrate 4′ on the chip mountingside to prevent leakage of sealing resin in the resin sealing step 28′(FIG. 85).

These dam pieces 34′ are formed by hardening an epoxy coating resin orthe like.

In the CSP18′, as the sealing parts 5′ formed in the resin sealing step28′ are not cut during the cutting 33′ (FIG. 85), a sealing resincomprising 50 weight percent or more of silica can be used as sealingmaterial.

Also, in the CSP18′, the two opposite side faces 1 c′ parallel to thelongitudinal direction of the semiconductor chip 1′ are not sealed andare exposed.

The remaining features of the construction of the CSP18′ according tothe thirteenth embodiment and of its method of manufacture are identicalto those of the CSP12′ of the seventh embodiment, so their descriptionwill not be repeated.

The advantages of the CSP18′ of the thirteenth embodiment and its methodof manufacture are as follows.

In the CSP18′, as the dam pieces 34′ are provided in the substrateprotruding parts 4 b′ of the thin film wiring substrate 4′ to preventleakage of sealing resin in the resin sealing step 28′, the sealingresin need not be cut, and the contour of the CSP18′ can be madecompact.

Further, as sealing resin is not cut in the cutting step 33′, a sealingresin comprising 50 weight percent or more of silica may be used.

The contraction factor of the sealing resin in the resin material curebake step 29′ shown in FIG. 85 is thereby reduced, and residual stressin the sealing resin is reduced.

The remaining advantages of the CSP18′ according to the thirteenthembodiment and its method of manufacture are identical to those of theCSP12′ of the seventh embodiment, so their description will not berepeated.

Embodiment 14

FIG. 111 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a fourteenth embodiment ofthis invention. FIGS. 112(a) to 121(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 111. FIG. 112(a) isa cross-sectional view through a line 112A-112A in FIG. 111, FIG. 112(b)is a cross-sectional view through a line 112B-112B in FIG. 111, FIG.112(c) is a cross-sectional view through a line 112C-112C in FIG. 111.

A CSP19′ (semiconductor device) according to the fourteenth embodimentis a peripheral pad fan-in CSP as is the CSP18′ of the eighth embodimentshown in FIG. 109. It has a substantially identical structure to that ofthe CSP18′, however a difference from the CSP18′ of the thirteenthembodiment is that the dam pieces 34′ provided on the surfaces of thesubstrate protruding parts 4 b′ of the thin film wiring substrate 4′ onthe chip mounting side, are formed in the shape of a frame surroundingthe entire periphery of the substrate protruding parts 4 b′.

The elastomer 3′ in the CSP19′ according to the fourteenth embodimentdoes not therefore comprise the elastomer protruding parts 3 b′ (FIG.109).

As the dam pieces 34′ are formed in the shape of a frame over the wholeouter periphery of the substrate protruding parts 4 b′, in the CSP19′according to the fourteenth embodiment, the resin sealing 28′ isperformed over all the four side faces 1 c′ of the semiconductor chip1′.

The remaining features of the construction of the CSP14′ according tothe fourteenth embodiment and of its method of manufacture are identicalto those of the CSP13′ of the eighth embodiment, so their descriptionwill not be repeated.

The advantages of the CSP14′ of the ninth embodiment and its method ofmanufacture are as follows.

In the CSP19′, as all of the surfaces of the elastomer 3′ are covered,the same advantages as when the side faces 3 a′ of the elastomer 3′ areexposed cannot be obtained. However as all of the side faces 1 c′, 3 a′of the semiconductor chip 1′ and elastomer 3′ are covered so as to formthe sealing parts 5′, and all of the peripheral sealing parts 5′ aredirectly joined to the substrate protruding parts 4 b′ of the thin filmwiring substrate 4′, the seal properties (humidity resistance) of thesemiconductor chip 1′ are improved.

The remaining advantages of the CSP19′ according to the fourteenthembodiment and its method of manufacture are identical to those of theCSP18′ of the thirteenth embodiment, so their description will not berepeated.

Embodiment 15

FIG. 113 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a fifteenth embodiment ofthis invention. FIGS. 114(a) to 114(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 113. FIG. 114(a) isa cross-sectional view through a line 114A-114A in FIG. 113, FIG. 114(b)is a cross-sectional view through a line 114B-114B in FIG. 113, FIG.114(c) is a cross-sectional view through a line 114C-114C in FIG. 113.

A CSP40′ (semiconductor device) according to the embodiment is aperipheral pad fan-in CSP as is the CSP16′ of the eleventh embodimentshown in FIG. 103. It has a substantially identical structure to that ofthe CSP16′, however a difference from the CSP16′ of the eleventhembodiment is that seal openings 4 m′, 3 f′ are provided at positionscorresponding to the two opposite side faces 1 c′ in the longitudinaldirection of the semiconductor chip 1′ (FIG. 114(c)) in the substrateprotruding parts 4 b′ of the thin film wiring substrate 4′ and in theelastomer protruding parts 3 b′ of the elastomer 3′ in addition to theopenings 4 e′ exposing the electrode pads 1 b′, as shown in FIG. 113.

Specifically, the two opposite openings 4 e′ and the two oppositeopenings 3 c′ are provided at positions exposing the electrode pads 1 b′on both sides of the semiconductor chip 1′, the two seal openings 4 m′and the two seal openings 3 f′ are provided at opposite positions in adirection at right angles to the openings 4 e′, 3 c′, and the thin filmwiring substrate 4′ and elastomer 3′ are formed in substantially thesame shape.

Hence, when the resin sealing 28′ shown in FIG. 85 is performed, sealingresin can be applied through the openings 4 e′, the openings 3 c′, theseal openings 4 m′ and the seal openings 3 f′ from the top surface ofthe thin film wiring substrate 4′.

Therefore, the four side faces 1 c′ of the semiconductor chip 1′ can becovered by sealing resin by this bonding method.

Further, as the elastomer 3′ comprises the elastomer protruding parts 3b′ which protrude beyond the four sides of the semiconductor chip 1′,the resin sealing 28′ can be performed on all the four side faces 1 c′of the semiconductor chip 1′.

The remaining features of the construction of the CSP40′ according tothe fifteenth embodiment and of its method of manufacture are identicalto those of the CSP16′ of the eleventh embodiment, so their descriptionwill not be repeated.

The advantages of the CSP40′ of the fifteenth embodiment and of itsmethod of manufacture are as follows.

In the CSP40′, as all the four side faces 1 c′ of the semiconductor chip1′ are sealed, the seal properties (humidity resistance) of thesemiconductor chip 1′ are improved.

Also, as leakage of sealing resin in the resin sealing step 28′ isprevented by the elastomer protruding parts 3 b′, sealing resin is notcut in the cutting step 33′, and the contour of the CSP40′ can be madecompact.

As sealing resin can be applied to four positions, i.e. one of theopenings 3 c′, one of the openings 4 e′, the seal opening 3 f′ and theseal opening 4 m′, from the same direction, the sealing step is madeeasier and productivity is improved.

The remaining advantages of the CSP40′ according to the fifteenthembodiment and of its method of manufacture are identical to those ofthe CSP16′ of the eleventh embodiment, so their description will not berepeated.

Embodiment 16

FIG. 115 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a sixteenth embodiment ofthis invention. FIGS. 116(a) to 116(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 115. FIG. 116(a) isa cross-sectional view through a line 116A-116A in FIG. 115, FIG. 116(b)is a cross-sectional view through a line 116B-116B in FIG. 115, FIG.116(c) is a cross-sectional view through a line 116C-116C in FIG. 115.

A CSP41′ (semiconductor device) according to the eleventh embodiment isa peripheral pad fan-in CSP as is the CSP40′ of the fifteenth embodimentshown in FIG. 113. It has a substantially identical structure to that ofthe CSP40′; however, a difference from the CSP40′ of the fifteenthembodiment is that when the CSP41′ is assembled, the elastomer 3′ isformed sufficiently thicker than the elastomer 3′ of the CSP40′ to theextent that the four side faces 1 c′ of the semiconductor chip 1′ aresurrounded by the protruding parts 3 b′ of the elastomer 3′ via thesealing parts 5′, as shown in FIG. 116.

In the CSP41′, the elastomer 3′ is formed of a porous fluoride resin sothat it can be formed thick.

Hence, in the CSP41′ of the sixteenth embodiment, the semiconductor chip1′ is attached so that the outer side faces 1 c′ on its outer peripheryare surrounded by the elastomer protruding parts 3 b′ of the elastomer3′ via the sealing parts 5′, as shown in FIG. 116(c).

Herein, the method of attaching (fixing) the semiconductor chip 1′ shownin FIG. 116(c) will be described.

To perform the chip attachment step 24′ shown in FIG. 85, thesemiconductor chip 1′ is pushed into the elastomer 3′ by making use ofthe fact that the elastomer 3′ is a porous fluoride resin.

As the elastomer 3′ is a porous fluoride resin, it can be easilydepressed under a comparatively small load.

The thickness of the elastomer 3′ directly underneath the semiconductorchip 1′ can, therefore, be made much smaller than the thickness of theouter periphery of the semiconductor chip 1′.

As a result, the semiconductor chip 1′ can be formed into a structurewherein the side faces 1 c′ on the outer periphery are surrounded by theelastomer protruding parts 3 b′ formed all around the periphery.

Sealing resin is then applied through the openings 4 e′ of the thin filmwiring substrate 4′ and the openings 3 c′ of the elastomer 3′, andthrough the seal openings 4 m′ of the thin film wiring substrate 4′ andthe seal openings 3 f′ of the elastomer 3′.

The sealing parts 5′ are thereby formed as a bridge between theperiphery of the main surface 1 a of the semiconductor chip 1′ and thefour side faces 1 c′, and between the substrate protruding parts 4 b′,elastomer protruding parts 3 b′ and semiconductor chip 1′.

The remaining features of the construction of the CSP41′ according tothe sixteenth embodiment and of its method of manufacture are identicalto those of the CSP40′ of the fifteenth embodiment, so their descriptionwill not be repeated.

The advantages of the CSP41′ of the sixteenth embodiment and its methodof manufacture are as follows.

In the CSP41′, as the elastomer 3′ is a porous fluoride resin, and asthe thickness of the elastomer 3′ directly underneath the semiconductorchip 1′ can be made much smaller than that of the outer periphery of thesemiconductor chip 1′, the semiconductor chip 1′ can be attached so thatthe side faces 1 c′ on the outer periphery of the semiconductor chip 1′are surrounded by the elastomer protruding parts 3 b′.

Hence, flow of sealing resin to the outside during the resin sealingstep 28′ of FIG. 85 is prevented by the elastomer protruding parts 3 b′and it is unnecessary to cut the sealing resin, so the CSP41′ may bemade compact.

The remaining advantages of the CSP41′ according to the sixteenthembodiment and its method of manufacture are identical to those of theCSP40′ of the fifteenth embodiment, so their description will not berepeated.

Embodiment 17

FIG. 117 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to a seventeenth embodiment ofthis invention. FIGS. 118(a) to 118(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 117. FIG. 118(a) isa cross-sectional view through a line 118A-118A in FIG. 117, FIG. 118(b)is a cross-sectional view through a line 118B-118B in FIG. 117, FIG.118(c) is a cross-sectional view through a line 118C-118C in FIG. 117.

A CSP42′ (semiconductor device) according to the seventeenth embodimentis a peripheral pad fan-in CSP as is the CSP40′ of the fifteenthembodiment shown in FIG. 113. It has a substantially identical structureto that of the CSP40′; however, a difference from the CSP40′ of thefifteenth embodiment is that the electrode pads 1 b′ are formed on theperiphery of the four sides of the main surface 1 a′ of thesemiconductor chip 1′.

As the four openings 4 e′ and four openings 3 c′ are respectively formedin the thin film wiring substrate 4′ and elastomer 3′ at correspondingidentical positions, the electrode pads 1 b′ on the four sides of thesemiconductor chip 1′ can be exposed by these openings 4 e′, 3 c′.

Sealing resin is applied through these four holes 4 e′, 3 c′ in theresin sealing step 28′ so as to form the sealing parts 5′ around thefour openings 4 e′, 3 c′.

The remaining features of the construction of the CSP42′ according tothe seventeenth embodiment and of its method of manufacture areidentical to those of the CSP40′ of the fifteenth embodiment, so theirdescription will not be repeated.

The advantages of the CSP42′ of the seventeenth embodiment and itsmethod of manufacture are as follows.

In the CSP42′, even when the electrode pads 1 b′ are provided on theperiphery of the four sides of the main surface 1 a′ of thesemiconductor chip 1′, the four openings 4 e′ and the four openings 3 c′are respectively formed in the thin film wiring substrate 4′ andelastomer 3′. Therefore, by performing the resin sealing 28′ through thefour openings 4 e′ and the four openings 3 c′, the humidity resistanceis made more reliable, and a compact CSP42′ can be obtained.

The remaining advantages of the CSP42′ according to the seventeenthembodiment and its method of manufacture are identical to those of theCSP40′ of the fifteenth embodiment, so their description will not berepeated.

Embodiment 18

FIG. 119 is a plan view through the sealing parts of a typical structureof a semiconductor device (CSP) according to an eighteenth embodiment ofthis invention. FIGS. 120(a) to 120(c) are diagrams showing thestructure of the semiconductor device shown in FIG. 119. FIG. 120(a) isa cross-sectional view through a line 120A-120A in FIG. 119, FIG. 120(b)is a cross-sectional view through a line 120B-120B in FIG. 119, FIG.120(c) is a cross-sectional view through a line 120C-120C in FIG. 119.

A CSP43′ (semiconductor device) according to the eighteenth embodimentis a peripheral pad fan-in CSP as is the CSP17′ of the twelfthembodiment shown in FIG. 105. It has a substantially identical structureto that of the CSP17′; however, a difference from the CSP17′ of thetwelfth embodiment is that the electrode pads 1 b′ are provided on theperipheries of the four sides of the main surface 1 a′ of thesemiconductor chip 1′.

Therefore, the four openings 4 e′ and the four openings 3 c′ are formedat corresponding positions in the thin film wiring substrate 4′ and theelastomer 3‘so that the electrode pads 1 b’ on the four sides of thesemiconductor chip 1′ are exposed.

Sealing resin is then applied via the four openings 4 e′ and the fouropenings 3 c′ in the resin sealing step 28′ so as to form the sealingparts 5′ in the four openings 4 e′, 3 c′.

The remaining features of the construction of the CSP43′ according tothe eighteenth embodiment and of its method of manufacture are identicalto those of the CSP17′ of the twelfth embodiment, so their descriptionwill not be repeated.

The advantages of the CSP43′ of the eighteenth embodiment and of itsmethod of manufacture are as follows.

In the CSP43′, by forming the four openings 4 e′ and the four openings 3c′ respectively in the thin film wiring substrate 4′ and the elastomer3′, a compact CSP43′ having improved humidity resistance can be obtainedeven if the electrode pads 1 b′ are provided on the peripheries of thefour sides of the main surface 1 a′ of the semiconductor chip 1′.

As the sealing resin can be applied to all of the four openings 4 e′, 3c′ from the same direction in the resin sealing step 28′, the sealingstep is made easier and productivity is improved.

Further, as the four side faces 1 c′ of the semiconductor chip 1′ aresealed by the elastomer protruding parts 3 b′ or the sealing parts 5′,the seal properties (humidity resistance) of the semiconductor chip 1′are improved.

The remaining advantages of the CSP43′ according to the eighteenthembodiment and of its method of manufacture are identical to those ofthe CSP17′ of the twelfth embodiment, so their description will not berepeated.

Embodiment 19

FIGS. 121(a) to 121(c) are diagrams of a typical structure of theunconnected lead of a semiconductor device according to a nineteenthembodiment of this invention. FIG. 121(a) is a cross-sectional view whenthe unconnected lead is bent, FIG. 121(b) and FIG. 121(c) arecross-sectional views when the unconnected lead is not bent.

According to the nineteenth embodiment, the semiconductor device (CSP)shown in Embodiments 6 to 18 has an unconnected lead 35′ (one of theleads 4 c′ which is not connected to the electrode pads 1 b′ of thesemiconductor chip 1′). This unconnected lead 35′ may or may not bebent.

Due to the unconnected lead 35′, the mode of the CSP can be changed overto change over functions, and different wiring configurations 4 d′ canbe set up by selecting either a connection or no connection for each ofthe leads 4 c′ for the same wiring pattern.

Therefore, if no connection is selected for the lead 4 c′, i.e., for theunconnected lead 35′, no connection of any kind is performed by thebonding tool (FIG. 94) in the bonding step.

The CSP17′ shown in Embodiment 12 will be taken as an example todescribe the unconnected lead 35′ shown in FIG. 121.

It will, however, be understood that the same features can be appliednot only to the twelfth embodiment, but to any of the sixth toeighteenth embodiments.

In the CSP17′ shown in FIG. 121(a), the unconnected lead 35′ is benttowards the electrode pad 1 b′ of the semiconductor chip 1′.

In this process, instead of making a connection with the bonding tool 7′in the bonding step, the lead 4 c′ is pressed down by the bonding tool7′ (i.e. in the direction of the main surface 1 a′ of the semiconductorchip 1′) to the extent that it does not touch the electrode pad 1 b′.

In both FIGS. 121(b) and (c), the unconnected lead 35′ is not bent.

The CSP17′ shown in FIG. 121(b) represents a state where the unconnectedlead 35′, which is not bent, is enclosed inside the sealing part 5′.

The CSP17 shown in FIG. 121(c) represents a state where the tip of theunconnected lead 35′, which is not bent, protrudes beyond the sealingpart 5′. As the surface of the sealing part 5′ is somewhat depressedwhen the sealing resin is cured, the unconnected lead 35′ is leftprojecting.

From the viewpoint of sealing properties, when the semiconductor device(CSP) comprises the unconnected lead 35′, it is desirable that theunconnected lead 35′ is bent in the direction of the main surface of thesemiconductor chip 1′ as shown in FIG. 121(a), but it is not absolutelynecessary to bend it and it may be unbent as shown in FIGS. 121(b),121(c).

The remaining features of the construction of the semiconductor device(CSP) according to the nineteenth embodiment are identical to those ofthe sixth to eighteenth embodiments, so their description will not berepeated.

The CSP does not necessarily comprise the unconnected lead 35′ describedin the nineteenth embodiment, this unconnected lead 35′ being useddepending on the function of the CSP.

It will be understood that the unconnected lead can also be used notonly in the twelfth embodiment, but also in any of the sixth toeighteenth embodiments, although not limited thereto.

Next, the effect obtained by the semiconductor device (CSP) according tothe nineteenth embodiment will be described.

In the CSP, a desired circuit can be constructed by selecting theconnected/unconnected leads 4 c′ using a common pattern, so it isunnecessary to provide separate wiring patterns for each product. Hence,common parts may be used for different CSPs, and, as a result, the CSPcan be manufactured at lower cost.

When the CSP has the unconnected lead 35′, by bending the unconnectedlead 35′ towards the electrode pad 1 b′ of the semiconductor chip 1′,the unconnected lead 35′ is not left exposed outside the sealing part 5′after resin sealing, so humidity resistance is improved. Also, bybending the unconnected lead 35′ towards the electrode pad 1 b′ of thesemiconductor chip 1′, the unconnected lead 35′ can be firmly sealedinside the sealing part 5′ even when the surface of the sealing part 5′is depressed.

This reduces the limitations on the sealing resin and increases thenumber of sealing resins that can be used.

Embodiment 20

FIGS. 122(a), 122(b), 122(c) are cross-sectional views showing a typicalstructure using a single layer surface wiring thin film wiring substratein a semiconductor device according to a twentieth embodiment of thisinvention, and FIGS. 123(a), 123(b), 123(c) are cross-sectional viewsusing a two-layer wiring thin film wiring substrate in a semiconductordevice according to the twentieth embodiment of this invention.

First, whereas the wiring 4 d′ of the thin film wiring substrate 4′ inthe semiconductor device (CSP) according to the sixth to nineteenthembodiments was single layer wiring formed only on the reverse side ofthe tape base material (elastomer side), according to the twentiethembodiment, however, the thin film wiring substrate 4′ is either singlelayer surface wiring wherein the wiring is formed only on the surfaceside of the tape (bump electrode side), or two layer wiring. This willnow be described using the sixth embodiment (CSP11′), seventh embodiment(CSP12′) and twelfth embodiment (CSP17′) as examples.

First, FIG. 122 shows the case where the thin film wiring substrate 4′is a single layer surface wired. FIG. 122(a) shows the case where theexternal structure of the semiconductor device is that of the tape (e.g.the CSP11′ of the sixth embodiment). FIG. 122(b) shows the case wherethe external structure of the semiconductor device is that of a sealedcontour (e.g. the CSP12′ of the seventh embodiment) FIG. 122(c) showsthe case where the external structure of the semiconductor device isthat of the elastomer (e.g. the CSP17′ of the twelfth embodiment).

Herein, the single layer surface wiring is the wiring 4 d′ formed on thetop surface of the tape base material 4 g′ of the thin film wiringsubstrate 4′, and a solder resist 4 r′ which is an insulating coating ofapproximately 10 to 30 μm thickness is formed at points excluding thebump lands 4 f′ on the tape base material 4 g′ (FIG. 108).

By using this single layer surface wiring, as the thickness of thesolder resist 4 r′ is only 10 to 30 μm which is relatively thin, soldercorrosion in the region of the joins of the bump lands of the bumpelectrodes 2′ is suppressed, and unevenness in the attachment height ofthe bump electrodes 2′ is reduced.

FIG. 123 shows the case where the thin film wiring substrate 4′ has twolayer wiring. FIG. 122(a) shows the case where the external structure ofthe semiconductor device is that of the tape (e.g. the CSP11′ of thesixth embodiment). FIG. 122(b) shows the case where the externalstructure of the semiconductor device is that of a sealed contour (e.g.the CSP12′ of the second embodiment). FIG. 122(c) shows the case wherethe external structure of the semiconductor device is that of theelastomer (e.g. the CSP17′ of the twelfth embodiment).

In the case of two layer wiring, the wiring 4 d′ is formed on the topsurface and reverse side of the tape base material 4 g′ of the thin filmwiring substrate. The wiring 4 d′ of the top and reverse sides iselectrically connected by through holes 4 w′, and a solder resist 4 r′which is an insulating coating of approximately 10 to 30 μm thickness isformed at points excluding the bump lands 4 f′ on the top surface of thetape base material 4 g′.

The remaining features of the construction of the semiconductor device(CSP) according to the twentieth embodiment are identical to those ofthe sixth to nineteenth embodiments, so their description will not berepeated.

The CSP does not necessarily have both the single layer surface wiringand the two-layer wiring described in the twentieth embodiment, and mayhave only the single layer surface wiring. Also, it is understood thatthese features may be applied not only to the sixth, seventh and twelfthembodiments, but to any of the sixth to nineteenth embodiments.

According to the twentieth embodiment, even when the number of bumpelectrodes 2′ increases and complex wiring has to be performed, thewiring 4 d′ is formed on the both the top and reverse sides of the tapebase material 4 g′ via the through holes 4 w′ so that the complex wiringis possible. As a result, the CSP can be manufactured even when thenumber of bump electrodes 2′ increases.

Embodiment 21

FIGS. 124(a), 124(b), 124(c), 124(d) are enlarged partial cross-sectionsshowing an example of a lead tip processing sequence in a semiconductordevice manufacturing method according to a twenty-first embodiment ofthis invention, as follows: FIG. 124(a) shows results before bonding,FIG. 124(b) shows results during bonding, FIG. 124(c) shows resultsafter bonding, and FIG. 124(d) shows results after sealing.

FIGS. 125(a) to 125(c) and FIGS. 126(a) to 126(c) are enlarged partialcross-sections showing another example of a lead tip processing sequencein a method of manufacturing a semiconductor device for comparison withthe lead tip processing shown in FIG. 124. The lead tip processingsequences thereof are as follows: (i) FIG. 125(a) shows results beforebonding, FIG. 125(b) shows results during bonding, and FIG. 125(c) showsresults after sealing; and (ii) FIG. 126(a) shows results beforebonding, FIG. 126(b) shows results during bonding, and FIG. 126(c) showsresults after sealing.

The twenty-first embodiment concerns the tip processing of the leads 4c′ during bonding in the semiconductor device (CSP) shown in the sixthto twentieth embodiments. The twenty-first embodiment will be describedusing the CSP17′ described in the twelfth embodiment, as an example.

First, in the comparative example shown in FIG. 125, as a distance Pshown in FIG. 125(a) is relatively long, the bonding tool 7′ is moved(lowered) to perform bonding as shown in FIG. 125(b), and then the resinsealing step 28′ (FIG.

85) is performed to form the sealing part 5′ as shown in FIG. 125(c)without tip processing of the leads 4 c′. In this case, as the distanceP shown in FIG. 125(a) is relatively long, the whole tip of the lead 4c′ after bonding is completely enclosed within the sealing part 5′, asshown in FIG. 125(c).

In the comparative example shown in FIG. 126, the distance P shown inFIG. 126(a) is relatively short. The bonding tool 7′ is moved (lowered)to perform bonding as shown in FIG. 126(b) and the resin sealing step28′ (FIG. 85) is performed to form the sealing part 5′ as shown in FIG.125(c) without tip processing of the lead 4 c′. In this case, as thedistance P shown in FIG. 126(a) is relatively short, tip processing ofthe lead 4 c′ after bonding is not performed as shown in FIG. 126(b), sothe tip of the lead 4 c′ after bonding protrudes beyond the sealing part5′ so that it is exposed as shown in FIG. 126(c).

On the other hand, in the CSP17′ of the twenty-first embodiment shown inFIG. 124, the bonding tool 7′ is lowered straight down toward theelectrode pad 1 b′ of the semiconductor chip 1′, and the electrode pad 1b′ and the lead 4 c′ of the thin film wiring substrate 4′ are thenelectrically connected by the pressing action of the bonding tool 7′, asshown in FIG. 124(b). The bonding tool 7′ is then moved in the directionof the tip of the lead 4 c′ (horizontal displacement) effectivelyparallel to the main surface 1 a′ of the semiconductor chip 1′, as shownin FIG. 124(c). Specifically, after bonding, the pressure of the bondingtool 7′ is removed, and the tip of the bonding tool 7′ is displaced by apredetermined amount (e.g. 10 to 300 μm, but preferably 30 to 200 μm) inthe direction of the tip of the lead 4 c′, then the resin sealing step28′ is performed so as to form the sealing part 5′ as shown in FIG.124(d). The splash angle near the tip of the lead 4 c′ can, therefore,be made small.

When the tip processing of the lead 4 c′ is performed, the bonding tool7′ may first be raised by a predetermined amount (e.g. 5 to 100 μm, butpreferably 10 to 60 μm) at the same time as the pressure of the bondingtool 7′ is removed, and then displaced horizontally by the predeterminedamount (e.g. 10 to 300 μm, but preferably 30 to 200 μm) in the directionof the tip of the lead 4 c′.

Regarding the tip processing of the lead 4 c′, the bonding tool 7′ maybe moved by the predetermined amount (e.g. 10 to 300 μm, but preferably30 to 200 μm) in the direction of the tip of the lead 4 c′ only when atleast the distance P is relatively short compared to a length L of theprojecting lead 4 c′ and a thickness E of the elastomer 3′ (e.g., P≦L-E,but preferably P≦L-E-100 μm). When the conditions regarding P, L, Eshown in FIG. 124(a) are not satisfied, it is not necessary to performtip processing of the lead 4 c′.

It will, moreover, be appreciated that it is not particularly necessaryto perform tip processing of the lead 4 c′ regardless of the distance P,length L and thickness E shown in FIG. 124(a).

The remaining features of the construction of the semiconductor device(CSP) according to the twenty-first embodiment are identical to those ofthe CSP shown in the sixth to twentieth embodiments, so theirdescription will not be repeated.

The tip processing of the lead 4 c′ described in the twenty-firstembodiment is not indispensable, and may be omitted.

It is understood that these features may be applied not only to thetwelfth embodiment, but also to any of the sixth to twentiethembodiments.

According to the sixteenth embodiment, regarding connection of the lead4 c′, the tip of the extra length of the lead 4 c′ is prevented fromprotruding more than is necessary above the top surface (main surface 1a′) of the semiconductor chip 1′ regardless of the positions of theelectrode pad 1 b′ on the semiconductor chip 1′ even when a lead 4 c′that is longer the required length is bonded.

Hence, the tip of the lead 4 c′ is prevented from being exposed outsidethe sealing part even after the sealing part 5′ has been formed by theresin sealing 28′ of the lead 4 c′ and electrode pad 1 b′ and, as aresult, the humidity resistance of the semiconductor device (CSP17′) ismore reliable.

Embodiment 22

FIG. 127 shows an elastomer specification showing a typical colorspecification of the elastomer (elastic structure) used in thesemiconductor device (CSP) according to a twenty-second embodiment ofthis invention.

In this twenty-second embodiment, the case will be described where acolored elastomer is used for the semiconductor device (CSP) shown inthe sixth to twenty-first embodiments.

Specifically, the elastomer 3′ of the CSP in the sixth to twenty-firstembodiments is colorless, and it is an effectively transparent bodywhich transmits light.

On the other hand, the elastomer 3′ (elastic structure) of thetwenty-second embodiment comprises a coloring agent in the adhesivelayer 3 e′ formed on both sides of the skeleton layer 3 d′ (FIG. 128described hereafter).

Specific examples of the specification of the colored elastomer 3′ arethe specification (1) and specification (2) shown in FIG. 127. Thecoloring agent used here is carbon.

In the colored elastomer specifications (1) and (2) shown in FIG. 127,the adhesive layer 3 e′ on both sides of the skeleton layer 3 d′contains the coloring agent; however, the invention is not limited tothis arrangement and the adhesive layer 3 e′ on only one side maycontain the coloring agent.

In the specifications (1) and (2) shown in FIG. 127 of the twenty-secondembodiment, the adhesive layers 3 e′ contain the coloring agent;however, the intermediate layer which is the skeleton layer 3 d′ mayalso contain the coloring agent, or both the adhesive layer 3 e′ and theskeleton layer 3 d′ may contain the coloring agent. In other words, itis sufficient if at least one of the parts comprising the elastomer 3′contains the coloring agent.

In the specifications (1) and (2) shown in FIG. 127, the coloring agentis composed of carbon particles; however, the coloring material is notlimited to this and may be another inorganic pigment or organic dye.

In the specification (1) and (2) shown in FIG. 127, the coloring agentis black carbon, but the coloring agent may be red, blue, green, pink,yellow or another color, or an intermediate color.

The remaining features of the construction of the semiconductor device(CSP) according to Embodiment 17 are identical to those of the CSP shownin Embodiments 6 to 16, so their description will not be repeated.

It should be noted that it is not absolutely necessary for the elastomer3′ in the CSP of the twenty-second embodiment to contain a coloringagent. However, by arranging for the elastomer 3′ to contain apredetermined amount of coloring agent according to the twenty-secondembodiment, the transmittance of the elastomer 3′ can be lowered withoutaffecting basic properties of the elastomer 3′ such as elastic modulus,thermal expansion coefficient, flame-retarding properties and humidityabsorption. In this way, the circuit of the semiconductor chip 1′ may beobscured from light. As a result, ultraviolet radiation, etc. which maycause incorrect operation of the semiconductor chip 1′ can be blocked,and stability of the electrical circuit of the CSP is enhanced.

By using carbon as coloring agent, a predetermined light obscuringeffect may be obtained by a small addition amount, so deterioration ofthe basic characteristics of the elastomer 3′ may be suppressed to theminimum. Also, by incorporating the coloring agent in at least one ofthe adhesive layers 3 e′ rather than the skeleton layer 3 d′ of theelastomer 3′, the elastomer 3′ can be colored at low cost.

Embodiment 23

FIGS. 128(a) to 128(h) are component charts showing examples of thedetailed composition of an elastomer in a semiconductor device accordingto a twenty-third embodiment of this invention. FIGS. 129(a) to 129(e)are component charts showing examples of the detailed composition of anelastomer in a semiconductor device according to the twenty-thirdembodiment of this invention. FIGS. 129(a) to 129(d) show 3-layerstructures, and FIG. 129(e) shows a 5-layer structure.

Embodiment 23 concerns specific materials of each component of theelastomer 3′ in the semiconductor device (CSP) of the sixth totwenty-second embodiments. Herein, FIGS. 128 and 129(a) to 129(d) showthe case where the elastomer 3′ comprises three layers, and FIG. 129(e)shows the case where the elastomer 3′ comprises five layers.

In the five layer structure, other thin adhesive layers 3 e′ are formedbetween the skeleton layer 3 d′ and the two (outermost) adhesive layers3 e′. According to Embodiment 23, a specific example of this five layerstructure is shown in FIG. 129(e), but in FIG. 128 and FIG. 129, it isparticularly effective to use this five layer structure when film layersare formed on both sides of the skeleton layer 3 d′ instead of coatinglayers in the elastomer 3′.

In an elastomer 3′ wherein the outer upper and lower layers are filmlayers, the use of this five layer structure further reduces therigidity of the film layers (adhesive layers 3 e′). As a result, therigidity of the elastomer 3′ is also reduced, so the elastomer easilymolds to the contour of the leads 4 c′ and the contact of the elastomer3′ is improved.

Herein, the materials of each component of the elastomer 3′ are notlimited to those of the twenty-third embodiment shown in FIG. 128 andFIG. 129, and the elastomer may also be a multi-layer structure whereinthe number of layers is not limited to three or five. It is preferablethat a porous material (for detailed structure of this porous material,refer to the sixth embodiment) comprising a 3-dimensional mesh structureis used for the skeleton layer 3 d′.

The remaining features of the construction of the semiconductor device(CSP) according to Embodiment 23 are identical to those of the CSP shownin Embodiments 6 to 22, so their description will not be repeated.

Embodiment 24

FIG. 130(a), 130(b) are diagrams showing typical thicknesses of theskeleton layer and adhesive layers in an elastomer of a semiconductordevice according to a twenty-fourth embodiment of this invention.

The twenty-fourth embodiment concerns the thicknesses of the adhesivelayers 3 e′ (FIG. 128 and FIG. 129) and the skeleton layer 3 d′ in theelastomer (elastic structure) of the semiconductor device (CSP) shown inthe sixth to twenty-third embodiments.

FIG. 130 shows the case where the elastomer 3′ comprises three layers.

First, in the elastomer 3′, the thickness of the tape side adhesivelayer 3 g′ is made thicker than the wiring 4 d′ of the tape basematerial 4 g′ (e.g., at least 1.2 times or at least 1.5 times).

Specifically, when for example the thickness of the wiring 4 d′ is 18μm, the thickness of the tape side adhesive layer 3 g′ is at least 21.6μm or, preferably, at least 27 μm.

Further, when for example the thickness of the wiring 4 d′ is 25 μm, thethickness of the tape side adhesive layer 3 g′ is at least 30 μm or,preferably, at least 37.5 μm.

FIG. 130(a) shows the case where the tape side adhesive layer 3 g′(adhesive layer adjacent to thin film wiring substrate) and the chipside adhesive layer 3 h′ have the same thickness. As an example, thethickness of these two layers is 30 μm and the thickness of the skeletonlayer 3 d′ which is the intermediate layer is 100 μm. If, for example,the thickness of the wiring 4 d′ is 18 μm, as the thickness of the upperand lower adhesive layers 3 e′ (herein, the tape side adhesive layer 3g′ and chip side adhesive layer 3 h′) is 30 μm, and the thickness of theskeleton layer 3 d′ is 100 μm, the total thickness of the elastomer 3′is 160 μm.

FIG. 130(b) shows the case where the tape side adhesive layer 3 g′(adhesive layer adjacent to thin film wiring substrate) is thicker thanthe chip side adhesive layer 3 h′. As an example, the thickness of thetape side adhesive layer 3 g′ is 75 μm, the thickness of the chip sideadhesive layer 3 h′ is 50 μm, and the thickness of the skeleton layerwhich is the intermediate layer is 25 μm. If, for example, the thicknessof the wiring 4 d′ is 18 μm, as the thickness of the tape side adhesivelayer 3 g′ is 75 μm, the thickness of the chip side adhesive layer 3 h′is 50 μm and the thickness of the skeleton layer 3 d′ is 25 μm, thetotal thickness of the elastomer 3′ is 150 μm.

It should be noted that the thicknesses given in FIG. 130 are onlyexamples, and the invention is not limited to them. Moreover, thethickness of the tape side adhesive layer 3 g′ and the chip sideadhesive layer 3 h′ may be identical or different.

According to Embodiment 24, by arranging the thickness of the tape sideadhesive layer 3 g′ to be greater (e.g. at least 1.2 times or at least1.5 times) than the thickness of the wiring 4 d′, undulations due to thewiring 4 d′ on the adhesive surface of the tape side base material 4 g′can be covered and, as a result, the contact of the tape side adhesivelayer 3 g′ is improved. This gives a CSP of high reliability. Also, byarranging the tape side adhesive layer 3 g′ and chip side adhesive layer3 h′ to have the same thickness, contact between the tape base material4 g′ and semiconductor chip 1′ is improved, and a high efficiency, lowcost elastomer 3′ can be manufactured. Finally, by arranging thethickness of the tape side adhesive layer 3 g′ to be greater than thethickness of the chip side adhesive layer 3 h′, even better contact canbe obtained with the undulations of the tape side adhesive layer 3 g′due to the wiring 4 d′ within the thickness conditions determined forthe elastomer overall. As a result, good adhesion is obtained and a CSPof high reliability can be manufactured.

The remaining features of the construction of the semiconductor device(CSP) according to Embodiment 24 are identical to those of the CSP shownin the Embodiments 6 to 23, so their description will not be repeated.

Embodiment 25

FIG. 131 is a base plane diagram showing the structure of the undersurface of a semiconductor device according to a twenty-fifth embodimentof this invention.

The twenty-fifth embodiment concerns the width of the wiring 4 d′ in thethin film wiring substrate 4′ in the semiconductor device (CSP) shown inthe sixth to twenty-fourth embodiments.

The twenty-fourth embodiment will be described taking the CSP17′ of thetwelfth embodiment as an example.

In the CSP17′ shown in FIG. 131, the wiring width of connecting parts 4s′ which connect with the bump lands 4 f′ of the wiring 4 d′ formed inthe thin film wiring substrate 4′, is formed wider than the wiring widthof the wiring 4 d′ at points remote from the connecting parts 4 s′, andthe wiring width of the connecting parts 4 s′ progressively becomesnarrower with increasing distance from the bump lands 4 f′.Specifically, in the wiring 4 d′ reaching the leads 4 c′ from the bumpland 4 f′ formed in the tape base material 4 g′ (FIG. 108), the wiringwidth of the connecting parts 4 s′ which connect with the bump lands 4f′ is wider than the wiring width of the wiring 4 d′ at points distantfrom these connecting parts 4 s′, these parts tapering off so that thewiring width of the connecting part 4 s′ gradually becomes narrower withincreasing distance from the bump lands 4 f′. In the CSP17′ shown inFIG. 131, the wiring width of all twelve of the connecting parts 4 s′ isformed wide, and these wide connecting parts 4 s′ progressively becomenarrower with increasing distance from the bump lands 4 f′.

The remaining features of the construction of the semiconductor device(CSP) according to Embodiment 25 are identical to those of the CSP ofthe Embodiments 6 to 24, so their description will not be repeated.

However, it is not absolutely necessary to form the connecting parts 4s′, such as described in the twenty-fifth embodiment, and they may beomitted.

Of the wiring formed on the tape base material 4 g′, the wiring 4 d′protruding from the connecting parts 4 s′ which are connected to thebump lands 4 f′ immediately adjacent to the leads 4 c′, is a relativelyshort distance away from the leads 4 c′. Therefore when a load acts onthe leads 4 c′ and wiring 4 d′, stress tends to concentrate in theconnecting parts 4 s′ which are connected to the bump lands 4 f′immediately adjacent to the leads. It is therefore desirable that whenthe connecting parts 4 s′ are formed, these connecting parts 4 s′ whichare connected to the bump lands 4 f′ immediately adjacent to the leads 4c′ are formed wider than other parts.

According to Embodiment 25, the connecting parts 4 s′ between the wiring4 d′ and bump lands 4 f′ are formed wide, so stress does not easilyconcentrate in these connecting parts 4 s′. Hence during a temperaturecycle, even if the tape base material 4 g′ and wiring 4 d′ deform due tothermal contraction and expansion, the connecting parts 4 s′ between thewiring 4 d′ and bump lands 4 f′ do not break.

It is of course understood that the features of this invention may beapplied not only to Embodiment 12, but also to Embodiments 6 to 24.

Embodiment 26

FIGS. 132(a) to 132(d) are figures each showing a typical structure of asemiconductor device according to a twenty-sixth embodiment of thisinvention. FIG. 132(a) is a base plan view, FIG. 132(b) is a side view,FIG. 132(c) is a plan view of which part has been cut away, and FIG.132(d) shows a front view. FIGS. 133(a) to 133(c) are diagrams of theconstruction of the semiconductor device shown in FIG. 132. FIG. 133(a)is a cross-sectional view through a line 133A-133A in FIG. 132. FIG.133(b) is a cross-sectional view through a line 133B-133B in FIG. 132.FIG. 133(c) is a cross-sectional view through a line 133C-133C in FIG.132. FIGS. 134(a) and 134(b) are enlarged partial cross-sections of thestructure of the semiconductor device shown in FIG. 133. FIG. 134(a) isa view of a part D in FIG. 133(b), FIG. 134(b) is a view of a part E inFIG. 133(c), and FIGS. 135(a) to 135(f) are diagrams each showing anexample of a method of manufacturing a thin film wiring substrate usedin the semiconductor device according to the twenty-sixth embodiment ofthis invention. FIGS. 135(a), 135(c), 135(e) are partial plan views, andFIG. 135(b), 135(d), 135(f) are, respectively, cross-sectional viewsshowing a section through lines 135A-135A, 135D-135D and 135F-135F.FIGS. 136(a) to 136(d) are diagrams each showing an example of a methodof manufacturing a thin film wiring substrate used in the semiconductordevice according to the twenty-sixth embodiment of this invention. FIGS.136(a), 136(c) are partial plan views, and FIGS. 136(b), 136(d) arerespectively cross-sectional views showing a section through lines136B-136B, 136D-136D. FIGS. 137(a) to 137(f) are diagrams each showingan example of a method of manufacturing a thin film wiring substrateused in the semiconductor device according to the twenty-sixthembodiment of this invention. FIGS. 137(a), 137(d) are partial planviews, FIGS. 137(b), 137(e) are, respectively, cross-sectional viewsshowing a section through lines 137B-137B, 137E-137E, and FIGS. 137(c),137(f) are, respectively, cross-sectional views showing a sectionthrough lines 137C-137C, 137F-137F. FIGS. 138(a) to 138(f) are diagramseach showing an example of a method of manufacturing a thin film wiringsubstrate used in the semiconductor device according to the twenty-sixthembodiment of this invention. FIGS. 138(a), 138(d) are partial planviews, FIGS. 138(b), 138(e) are, respectively, cross-sectional viewsshowing a section through lines 138B-138B, 138E-138E, and FIGS. 138(c),138(f) are respectively cross-sectional views showing a section throughlines 138C-138C, 138F-138F. FIGS. 139(a) to 139(f) are diagrams eachshowing an example of a method of manufacturing a thin film wiringsubstrate used in the semiconductor device according to the twenty-sixthembodiment of this invention. FIGS. 139(a), 139(d) are partial planviews, FIGS. 139(b), 139(e) are respectively cross-sectional viewsshowing a section through lines 139B-139B, 139E-139E, and FIGS. 139(c),139(f) are, respectively, cross-sectional views showing a sectionthrough lines 139C-139C, 139F-139F.

A semiconductor device (CSP51′) according to the twenty-sixth embodimentis a peripheral pad type fan-in CSP identical to the CSP17′ of thetwelfth embodiment shown in FIG. 105. It has a substantially identicalstructure to that of the CSP17′; however, differences from the CSP17′ ofthe twelfth embodiment are that the thin film wiring substrate 4′ doesnot comprise the base protruding parts 4 b′ shown in FIG. 105, and theelastomer 3′ (FIG. 132(a)) which is an elastic structure comprisesexposed parts 3 i′ which are exposed to the outside, as shown in FIG.132(b).

Specifically, whereas the CSP of Embodiments 6 to 25 is a structurewherein at least the thin film wiring substrate 4′ comprises substrateprotruding parts 4 b′ which protrude beyond the periphery of thesemiconductor chip 1′, the CSP51′ according to Embodiment 26 is astructure wherein the thin film wiring substrate 4′ does not comprisethe substrate protruding parts 4 b′.

The CSP51′, therefore, does not comprise the elastomer protruding parts3 b′ provided in the elastomer of the CSP17′ shown in FIG. 105.

Herein, the detailed structure of the CSP51′ according to thetwenty-sixth embodiment will be described.

The CSP51 comprises the elastomer 3′ (elastic structure) provided withthe exposed parts 3 i′ arranged on the main surface 1 a′ of thesemiconductor chip 1′ for exposing the electrode pads 1 b′ (connectionterminals), a substrate body 4 a′ provided with the wiring 4 d′ whereofone end is electrically connected to the electrode pads 1 b′ via theleads 4 c′ and the other ends are electrically connected to the bumpelectrodes 2′ (external terminals), the thin film wiring substrate 4′comprising the openings 4 e′ for exposing the electrode pads 1 b′, and asealing part 5′ for sealing the electrode pads 1 b′ of the semiconductorchip 1′ and the thin film wiring substrate 4′.

In the CSP51′ shown in FIG. 132, 20 of the bump electrodes 2′ areprovided.

The CSP51′ comprises the exposed parts 3 i′ of the elastomer 3′ (FIG.132(a)) on the two long side faces 51 a′ as shown in FIG. 132(b), therebeing four of the exposed parts 51 a′ on each of the two sides 51 a′ ofthe CSP51′.

The remaining features of the construction of the semiconductor device(CSP) according to Embodiment 26 are identical to those of the CSP17′ ofEmbodiment 12, so their description will not be repeated.

The method of manufacturing the CSP51′ according to the twenty-sixthembodiment will now be described.

First, as shown in FIG. 135 and FIG. 136, the elastomer 3′ joined to thesubstrate body 4 a′ comprising the wiring 4 d′ is manufactured, theopenings 4 e′ comprising the leads 4 c′ connected to the wiring 4 d′ areformed, and the thin film wiring substrate 4′ (FIG. 136(c)) wherein thesubstrate body 4 a′ is supported in a substrate frame 4 t′ by supporters3 j′ of the elastomer 3′ is prepared.

The method of manufacturing the thin film wiring substrate 4′ will bedescribed referring to FIG. 135 and FIG. 136.

The tape base material 4 g′ comprising a polyimide resin shown in FIG.135(a) is prepared. An adhesive is coated on the top surface, undersurface or both the top surface and under surface of the tape basematerial 4 g′ in order to attach the copper foil 4 h′ shown in FIG.135(c).

Next, reference holes 4 i′ for tape feed are formed at an approximatelyequal interval on both sides of the tape base material 4 g′.

Next, 20 of the bump openings 4 j′ are formed. Two of the wiring joinopenings 4 e′ and two of the long cutting holes 4 q′ are formed on bothsides by a punch die as shown in FIG. 135(a), and the copper foil 4 h′is laminated on the tape base material 4 g′ as shown in FIGS. 135(c),135(d).

The copper foil 4 h′ is formed into a desired shape by etching as shownin FIG. 135(e) so as to form the wiring pattern.

Next, the tape base material 4 g′ is attached to the elastomer 3′ asshown in FIGS. 136(a), 136(b).

The elastomer 3′ used in the twenty-sixth embodiment comprises four longsupporting members 3 j′ on each side (a total of eight on both sides) asshown in FIG. 136(a). These supporting members 3 j′ straddle the fourlong holes 4 q′ of the thin film wiring substrate 4′ and aresufficiently long to reach the substrate frame 4 t′. However, the numberof the supporting members 3 j′ is not limited to eight, and any numberis permitted. The number of these supporting members 3 j′ corresponds tothe number of exposed parts 3 i′ of the CSP51′. Hence, the elastomer 3′is attached to the thin film wiring substrate 4′, the body of theelastomer 3′ is attached to the substrate body 4 a′ of the thin filmwiring substrate 4′, and the eight supporting members 3 j′ of theelastomer 3′ are arranged to straddle the long holes 4 q′ of the thinfilm wiring substrate 4′ so as to attach them to the substrate frame 4t′.

Next, four suspension members 4 u′ supporting the substrate body 4 a′shown in FIG. 136(a) are cut so that the substrate body 4 a′ issupported in the substrate frame 4 t′ by the supporting members 3 j′ ofthe elastomer 3′.

In other words, the substrate body 4 a′ of the thin film wiringsubstrate 4′ shown in FIG. 136(c) is supported by the elastomer attachedto it.

As a result, the thin film wiring substrate 4′ to which the elastomer 3′is attached is formed as shown in FIGS. 136(c), 136(d) and FIGS. 137(a)to 137(c).

Next, the electrode pads 1 b′ (FIG. 132) of the semiconductor chip 1′are exposed by the openings 4 e′ of the thin film wiring substrate 4′,and the main surface 1 a′ of the semiconductor chip 1′ and the elastomer3′ are joined.

In other words, the semiconductor chip 1′ is attached to the elastomer3′ as shown in FIGS. 137(d) to 137(f).

Next, the electrode pads 1 b′ of the semiconductor chip 1′ (FIG. 132)and the corresponding leads 4 c′ of the thin film wiring substrate 4′are electrically connected, as shown in FIG. 138(a).

Next, the resin sealing 28′ (FIG. 85) of the electrode pads 1 b′ of thesemiconductor chip 1′ and the leads 4 c′ of the thin film wiringsubstrate 4′ is performed by a potting method using sealing resin asshown in FIGS. 138(d) to 138(f) so as to form the sealing parts 5′.

The resin sealing 28′ may be performed also by the transfer mold method.

Next, a bump pole material is supplied to the bump openings 4 j′ of thesubstrate body 4 a′, and the bump electrodes 2′ are formed as shown inFIG. 139(a)-139(c) by passing the assembly through a reflow furnace, notshown.

In this way, the wiring 4 d′ of the substrate body 4 a′ (FIG. 132 orFIG. 133) is electrically connected to the bump electrodes 2′.

Next, the supporting members 3 j′ of the elastomer 3′ are cut so as toseparate them from the substrate frame 4 t′ of the substrate body 4 a′,and the exposed parts 3 i′ (FIG. 139(e)) of the elastomer 3′ formed bythe cut supporting members 3 j′, are thereby exposed.

Therefore, the CPS51′ as shown in FIGS. 139(d) to 139(f) or FIG. 132 canbe produced.

The remaining features of the method of manufacture of the CSP51′ areidentical to those of the CSP17′ of the twelfth embodiment, so theirdescription will not be repeated.

It will be understood that the techniques of the aforesaid Embodiments19 to 25 may be applied also to the CSP51′ of Embodiment 26.

The advantages of the CSP51′ of the twenty-sixth embodiment and of itsmethod of manufacture are as follows.

If the internal pressure of the elastomer rises due to expansion ofwater vapor and gas during solder reflow when the bump electrodes areformed, this gas (vapor) can escape from the exposed parts 3 i′ of theelastomer 3′ to the outside via a gas escape path 36′ as shown in FIG.132(a) (gas can escape from any of the eight exposed parts 3 i′).

In other words, gas can be released by the exposed parts 3 i′ of theelastomer 3′.

The occurrence of the popcorn phenomenon wherein the sealing part 5′ isruptured, is thereby prevented.

As a result, reliability of the CSP51′ is improved.

The remaining advantages of the method of manufacture of the CSP51′according to the twenty-sixth embodiment are identical to those of theCSP17′ of the twelfth embodiment, so their description will not berepeated.

Embodiment 27

FIGS. 140(a) to 140(c) show examples of the structure of a semiconductordevice according to a twenty-seventh embodiment. FIG. 140(a) is a sideview, FIG. 140(b) is a plan view, FIG. 140(c) is a front view.

A CSP52′ (semiconductor device) according to the twenty-seventhembodiment is a peripheral pad type fan-in CSP as is the CSP51′ of thetwenty-sixth embodiment shown in FIG. 132. It has a substantiallyidentical structure to that of the CSP51′; however, differences from theCSP51′ of the twenty-sixth embodiment are that all of the side faces ofthe elastomer 3′ (FIG. 132) are exposed in the side faces 52 a′ of theCSP52′, as shown in FIG. 140. In other words, in the CSP52′, all theside faces of the elastomer 3′ are exposed as the exposed parts 3 i′after manufacture is complete, as shown in FIG. 140(a).

The remaining features of the construction of the CSP52′ according tothe twenty-seventh embodiment are identical to those of the CSP51′ ofthe twenty-sixth embodiment, so their description will not be repeated.

It will be understood that the techniques of the aforesaid Embodiments19 to 25 may be applied also to the CSP52′ of Embodiment 27.

The advantages of the CSP52′ of the twenty-seventh embodiment and of itsmethod of manufacture are as follows.

In the CSP52′, as the entire side faces of the elastomer 3′ form theexposed parts 3 i′, the exposed surface area of the elastomer 3′ isincreased. Hence, the gas release effect due to the exposed areas 3 i′of the elastomer 3′ is enhanced. As a result, the reliability of theCSP52′ is further improved.

The remaining features of the CSP52′ according to the twenty-seventhembodiment and of its method of manufacture are identical to those ofthe CSP51′ of the twenty-sixth embodiment, so their description will notbe repeated.

Embodiment 28

FIGS. 141(a) to 141(d) are plan views each showing a typical structureof a semiconductor device according to a twenty-eighth embodiment ofthis invention. FIG. 141(a) is a plan view, FIG. 141(b) is a side view,FIG. 141(c) is a plan view, and FIG. 141(d) is a front view. FIGS.142(a) to 142(b) are diagrams each showing an example of a state whensealing is complete in a method of manufacturing the semiconductordevice according to the twenty-eighth embodiment of this invention. FIG.142(a) is a plan view, FIG. 142(b) is a base plan view. FIGS. 143(a) to143(c) show cross-sections of the plan view shown in FIG. 142(a). FIGS.143(a) is a cross-sectional view through a line 143A-143A, FIG. 143(b)is a cross-sectional view through a line 143B-143B, FIG. 143(c) is across-sectional view through a line 143C-143C. FIGS. 144(a) to 144(c)are diagrams each showing an example of a state when sealing is completein a method of manufacturing the semiconductor device according to thetwenty-eighth embodiment of this invention. FIG. 144(a) is a plan view,FIG. 144(b) is a side view, FIG. 144(c) is a base plan view. FIG. 145 isa schematic diagram showing an example of a gas release state in thesemiconductor device according to the twenty-eighth embodiment.

A CSP53′ (semiconductor device) according to the twenty-eighthembodiment is a peripheral pad type fan-in CSP as is the CSP51′ of thetwenty-sixth embodiment shown in FIG. 132. It has a substantiallyidentical structure to that of the CSP51′; however, differences from theCSP51′ of the twenty-sixth embodiment are that the sealing parts 5′ areformed only in the vicinity of the two ends of the semiconductor chip 1′as shown in FIG. 141(a). Hence, the device comprises the exposed parts 3i′ corresponding to the entire side faces of the elastomer 3′, and theexposed parts 3 i′ formed by exposing the area in the vicinity of thecenter on the left and right of the peripheral part on the top surfaceand under surface of the device, as shown in FIGS. 141(b), 141(c).

In other words, in the CSP53′, the resin sealing 28′ is not performedover all the side faces 1 c′ of the semiconductor chip 1′, but only inthe vicinity of the electrode pads 1 b′ (FIG. 132).

Herein, FIG. 142 and FIG. 143 show the structure obtained when the resinsealing 28′ is complete in the process of manufacturing the CSP53′. FIG.142(a) shows a plan view, and FIG. 142(b) is a base view seen from theunder surface.

The sealing parts 5′ are formed on the short side faces 1 c′ of thesemiconductor chip 1′ and at both ends of the long side faces 1 c′, asshown in FIG. 142(b). As they are not formed in the vicinity of thecenter of the side faces 1 c′, the areas in the vicinity of the centeron the left and right of the peripheral part of the top surface andunder surface of the elastomer 3′ are exposed.

In the CSP53′ according to the twenty-eighth embodiment, the shape ofthe elastomer 3′ is substantially identical to that of the tape basematerial 4 g′, as shown in FIG. 142. In other words, the shape of theelastomer 3′ is made to effectively fit that of the thin film wiringsubstrate 4′ including the openings 4 e′, long holes 4 q′ and suspensionmembers 4 u′ of the thin film wiring substrate 4′.

FIG. 144 shows the situation after resin sealing when the suspensionmembers 4 u′ of the thin film wiring substrate 4′ and suspension pieces3 k′ of the elastomer 3′ shown in FIG. 142 are cut so as to separate thesubstrate body 4 a′ from the substrate frame 4 t′.

The remaining features of the CSP53′ according to the twenty-eighthembodiment and of its method of manufacture are identical to those ofthe CSP51′ of the twenty-sixth embodiment, so their description will notbe repeated.

It will be understood that the techniques of the aforesaid Embodiments19 to 25 may be applied also to the CSP53′ of Embodiment 28.

The advantages of the CSP53′ of the twenty-eighth embodiment and of itsmethod of manufacture are as follows.

In the CSP53′, the areas in the vicinity of the center on the left andright of the peripheral part of the top surface and under surface of theelastomer 3′ are exposed, and as the exposed surface area of theelastomer 3′ is increased with the addition of the exposed parts 3 i′ atthe cut positions. Therefore, the gas release effect is further enhancedwhen gas escapes via the gas escape path 36′ shown in FIG. 145.

Also, by forming the shape of the elastomer 3′ substantially the same asthat of the tape base material 4 g′, the strength of the thin filmwiring substrate 4′ in the CSP53′ is increased. As a result, defects inthe CSP53′ are reduced, and the yield is increased.

The remaining features of the CSP53′ according to the twenty-eighthembodiment and of its method of manufacture are identical to those ofthe CSP51′ of the twenty-sixth embodiment so their description will notbe repeated.

Embodiment 29

FIGS. 146(a) to 146(e) is a diagram of a typical structure of asemiconductor device according to a twenty-ninth embodiment of thisinvention. FIG. 146(a) is a base plan view, FIG. 146(b) is a side view,FIG. 146(c) is a plan view, FIG. 146(d) is a front view, FIG. 146(e) isa section through a line 146E-146E in FIG. 146(c).

A CSP54′ (semiconductor device) according to the twenty-ninth embodimentis a peripheral pad type fan-in CSP as is the CSP51′ of the twenty-sixthembodiment shown in FIG. 132. It has a substantially identical structureto that of the CSP51′; however, differences from the CSP51′ of thetwenty-sixth embodiment are that openings 4 v′ for exposing theelastomer 3′ are provided in the thin film wiring substrate 4′ as shownin FIGS. 146(c), 1465(e), and that there are no positions exposing theelastomer 3′ other than the openings 4 v′ as shown in FIG. 146.

In the CSP54′ according to the twenty-ninth embodiment, the two openings4 v′ are provided inside the substrate body 4 a′ of the thin film wiringsubstrate 4′. As a result, when the CSP54′ is assembled, the elastomer3′ is exposed via these openings 4 v′. Therefore, the exposed parts 3 i′of the elastomer 3′ are formed by the openings 4 v′. In the CSP54′,there are no positions exposing the elastomer 3′ other than the openings4 v′. In other words, the resin sealing 28′ is performed over all theside faces 1 c′ without exposing the side faces 1 c′ of thesemiconductor chip 1′ as shown in FIG. 146(a) to 146(d).

In the CSP54′ according to the twenty-ninth embodiment, the openings 4v′ are formed in the substrate body 4 a′ of the thin film wiringsubstrate 4′, and they may be formed at any position provided that theelastomer 3′ is exposed after the CSP54′ is assembled. Moreover, thereis no particular limitation on the number of the openings 4 v′.

The remaining features of the construction of the CSP54′ according tothe twenty-ninth embodiment and of its method of manufacture areidentical to those of the CSP51′ of the twenty-sixth embodiment, sotheir description will not be repeated.

It will be understood that the techniques of the aforesaid Embodiments19 to 25 may be applied also to the CSP54′ of Embodiment 29.

The advantages of the CSP54′ of the twenty-ninth embodiment and of itsmethod of manufacture are as follows.

In the CSP54′, the resin sealing 28′ is performed over all the sidefaces 1 c′ of the semiconductor chip 1′, so the sealing properties ofthe semiconductor chip 1′ are improved. As a result, defects in thesemiconductor chip 1′ are reduced, and the reliability of the CSP54′ isimproved.

Also, as the openings 4 v′ are provided in the thin film wiringsubstrate 4′, gas can be released via these openings 4 v′ even when theresin sealing 28′ is performed over all the side faces 1 c′ of thesemiconductor chip 1′. Therefore, gas release from the elastomer 3′ isenhanced while the sealing properties of the semiconductor chip 1′ areimproved.

The remaining advantages of the method of manufacture of the CSP54′according to the twenty-ninth embodiment are identical to those of theCSP51 of the twenty-sixth embodiment, so their description will not berepeated.

Embodiment 30

FIGS. 147(a) to 147(c) are diagrams of a typical structure of asemiconductor device according to a thirtieth embodiment of thisinvention. FIG. 147(a) is a plan view, FIG. 147(b) is a side view, andFIG. 147(c) is a base plan view. FIG. 148 is a partial plan view showingan example of a sealing completion state in a method of manufacturingthe semiconductor device according to the twenty-fifth embodiment ofthis invention. FIGS. 149(a) and 149(b) are views showing cross-sectionsthrough the partial plan view shown in FIG. 148. FIG. 149(a) is across-section through the line 149A-149A, and FIG. 149(b) is across-section through the line 149B-149B in FIG. 148. FIGS. 150(a) and150(b) are partial plan views each showing an example of a sealingcompletion state in a method of manufacturing the semiconductor deviceaccording to the thirtieth embodiment of this invention. FIG. 150(a) isa base plan view, and FIG. 150(b) is a base plan view of a state withthe semiconductor chip removed. FIG. 151 is a schematic diagram showingan example of a gas release state in a semiconductor device according tothe thirtieth embodiment of this invention.

A CSP55′ (semiconductor device) according to the thirtieth embodiment isa structure wherein pads are formed on the chip periphery, and the padelectrodes 1 b′ are formed both inside and outside the chip 1′ as shownin FIG. 147. Hereafter, this type of CSP will be referred to as afan-in/fan-out CSP. Differences from the CSP51′ of the twenty-sixthembodiment are that electrode pads 1 b′ are provided on the periphery ofthe four sides of the main surface 1 a′ of the semiconductor chip 1′,and the bump electrodes 2′ which are external terminals are arrangedinside (substrate body 4 a′) and outside (substrate protruding parts 4b′) the semiconductor chip 1′.

The CSP55′ comprises an elastomer 3′ comprising the exposed parts 3 i′for exposing the electrode pads 1 b′ (connection terminals) arranged onthe main surface 1 a′ of the semiconductor chip 1′, and the elastomerprotruding parts 3 b′ (elastic structure protruding parts) whichprotrude beyond the periphery of the semiconductor chip 1′, the thinfilm wiring substrate 4′ comprising the substrate body 4 a′ providedwith the wiring 4 d′ whereof one end is electrically connected to theelectrode pads 1 b′ via the leads 4 c′ (FIG. 132) and the other end iselectrically connected to the bump electrodes 2′, and the substrateprotruding parts 4 b′ provided with the openings 4 e′ for exposing theelectrode pads 1 b′ (FIG. 132), these protruding parts protruding beyondthe openings 4 e′ and the semiconductor chip 1′, and the sealing parts5′ for sealing the electrode pads 1 b of the semiconductor chip 1′ andthe leads 4 c′ of the thin film wiring substrate 4′. The thin filmwiring substrate 4′ and the elastomer 3′ are formed in approximately thesame size, and the bump electrodes 2′are provided in the substrate body4 a′.

Therefore, in the CSP55′ the thin film wiring substrate 4′comprises thesubstrate protruding parts 4 b′ formed in a one-piece construction withthe substrate body 4 a′ and its outer periphery, the bump electrodes 2′being provided in these substrate protruding parts 4 b′ outside thesemiconductor chip 1′.

FIG. 148 to FIG. 150 show the structure of the CSP55′ when the resinsealing 28′ is complete. FIG. 148 is a plan view, FIG. 148 is across-sectional view, FIG. 150(a) is a base plan view seen from theunder surface, and FIG. 150(b) is a view of the tape base material 4 g′seen from the under surface through the semiconductor chip 1′.

The substrate body 4 a′ and substrate protruding parts 4 b′ areconnected and supported by the suspension members 4 u′ of the four anglepieces of the substrate body 4 a′, via the four openings 4 e′ (FIG.149(a)) formed in the outer periphery of the substrate body 4 a′.

In the outer periphery of the substrate protruding parts 4 b′, the fourlong holes 4 q′ used for cutting are formed, and the substrateprotruding parts 4 b′ are supported in the substrate frame 4 t′ by thesuspension members 4 u′ of the four angle pieces.

The elastomer 3′ of the thirtieth embodiment is formed with a shapesubstantially fitting that of the substrate body 4 a′ and substrateprotruding parts 4 b′ in the thin film wiring substrate 4′ shown in FIG.148, as shown in FIG. 150(a).

Therefore, the elastomer protruding parts 3 b′ are provided which aresupported by the suspension pieces 3 k′ (FIG. 150(b)) and formed withessentially the same shape as that of the substrate protruding parts 4b′, and the four openings 3 c′ are formed with effectively the same sizeas that of the four openings 4 e′ of the thin film wiring substrate.

The sealing parts 5′ are formed only in the four openings 4 e′ of thethin film wiring substrate 4′, i.e. in the vicinity of the electrodepads 1 b′ of the semiconductor chip 1′, as shown in FIG. 149(a).

Therefore when assembly is complete, in the CSP55′ which is afan-in/fan-out structure, all points on the under surface of theelastomer 3′ excluding those covered by the semiconductor chip 1′(elastomer protruding parts 3 b′) and all of the side faces 1 a′ areexposed to form the exposed parts 3 i′, as shown in FIGS. 147(b),147(c).

FIG. 147 shows the state where, after resin sealing, the semiconductordevice is cut in the suspension members 4 u′ of the angle pieces of thesubstrate protruding parts 4 b′ of the thin film wiring substrate 4′shown in FIG. 148 so as to separate the substrate body 4 a′ andsubstrate protruding parts 4 b′ from the substrate frame 4 t′.

The remaining features of the construction of the CSP55′ according tothe thirtieth embodiment are identical to those of the CSP51′ of thetwenty-sixth embodiment, so their description will not be repeated.

The method of manufacturing the CSP55′ according to the thirtiethembodiment will now be described.

First, the substrate body 4 a′ comprising the wiring 4 d′ and thesubstrate protruding parts 4 b′ on its outer periphery are formed, theelastomer 3′ which has effectively the same shape as that of thesubstrate protruding parts 4 b′ and substrate body 4 a′ is joined to it,and the thin film wiring substrate 4′ comprising the openings 4 e′comprising the leads 4 c′ joined to the wiring 4 d′ is prepared.

Next, the main surface 1 a′ of the semiconductor chip 1′ and theelastomer 3′ are joined so as to expose the electrode pads 1 b′ (FIG.132) of the semiconductor chip 1′ in the openings 4 e′ of the thin filmwiring substrate 4′.

The electrode pads 1 b′ of the semiconductor chip 1′ are electricallyconnected to the corresponding leads 4 c′ of the thin film wiringsubstrate 4′.

Next, the resin sealing 28′ is applied to the electrode pads 1 b′ of thesemiconductor chip 1′ and the leads 4 c′ of the thin film wiringsubstrate 4′ to form the sealing parts 5′.

The state of the device when sealing is complete is shown in FIG. 148,FIG. 149 and FIG. 150.

Next, the bump electrodes 2′ are formed in the substrate body 4 a′ andsubstrate protruding parts 4 b′ so that they are electrically connectedto the wiring 4 d′.

The four suspension members 4 u′ in the outer angle pieces of thesubstrate protruding parts 4 b′ shown in FIG. 148 are cut so that thesubstrate body 4 a′ and substrate protruding parts 4 b′ are separatedfrom the substrate frame 4 t′.

The state of the device when cutting is complete is shown in FIGS.147(a), 147(b), 147(c).

The remaining features of the method of manufacturing the CSP55′according to the thirtieth embodiment are identical to those of theCSP51′ of the twenty-sixth embodiment, so their description will not berepeated.

It will be understood that the techniques of the aforesaid Embodiments19 to 25 may be applied also to the CSP55′ of Embodiment 30.

The advantages of the CSP55′ of the thirtieth embodiment and of itsmethod of manufacture are as follows.

In the CSP55′, even in a fan-in/fan-out structure, gas (vapor) can bereleased via the gas escape path 36′ through the suspension members 3 k′(FIG. 150(b)) provided in the elastomer 3′ as shown in FIG. 151.

The occurrence of the popcorn phenomenon which damages the sealing part5′ is thereby prevented, and as a result the reliability of the CSP55′is improved.

The remaining features of the CSP55′ according to the thirtiethembodiment and of its method of manufacture are identical to those ofthe CSP51 of the twenty-sixth embodiment, so their description will notbe repeated.

This invention has been described in detail based on the first tothirtieth embodiments; however, the invention is not limited to thesethirty embodiments and various modifications are possible within thescope and spirit of the invention.

For example, the specifications of the components shown in FIG. 84(a, b,c, d) and the process conditions shown in FIG. 85 are only examples ofoptimum conditions, and the invention is not necessarily limited to theexamples shown in FIG. 84 (a, b, c, d) and FIG. 85.

Further, in the aforesaid embodiments, although not limited thereto,although the case was primarily described where the semiconductor chip1′ is longitudinal (elongated rectangle) in shape, the semiconductorchip 1′ may also have a different plan view shape such as a square.

The electrode pads 1 b′ provided in the semiconductor chip 1′ are notnecessarily located at the two ends of the semiconductor chip 1′, andmay be provided in any other position provided that this position issituated on the outer periphery of the main surface 1 a′ of thesemiconductor chip 1′. They may for example be provided over the wholeof the outer periphery.

The number of the electrode pads 1 b′ and the number of bump electrodes2′ provided in the semiconductor chip 1′ is not limited to 12 or 20, andmay be a number less than 12, 13-19 or more than 20.

The shape of the openings 4 e′ of the thin film wiring substrate 4′ andthe openings 3 c′ of the elastomer 3′ is not limited to rectangular, andmay be another shape provided that the electrode pads 1 b′ of thesemiconductor chip 1′ can be exposed.

The semiconductor device described in the aforesaid embodiments may beused for example in a DRAM (Dynamic Random Access Memory), SDRAM(Synchronous DRAM) SRAM (Static RAM), RAMBUS, flash memory, ASIC(Application Specific IC), CPU (Central Processing Unit) or gate array,although not limited thereto. Typical applications of these devices aremodules and cards, but it will be understood that they may be applied toproducts other than modules and cards.

The techniques in the Embodiments 1-30, also, can be combined asrequired.

The number of the solder bumps serving as external connection terminalsof the semiconductor package and the bonding pads serving as externalterminals of the semiconductor chip electrically connected with thesolder bumps are not restricted only to those described in connectionwith the embodiments, but they may be properly modified depending on orin accordance with the specification of the packages, such as theintegrated circuits formed on the semiconductor chip.

Further, regarding the materials, for example, for the elastomer formingthe elastic structural material, the tape for the flexible wiringsubstrate, the wiring and lead plating, the solder resist serving as theinsulation film and the solder bump serving as a bump electrode, theinvention is also applicable in a case of using other materials havingrespective properties.

For example, as the solder resist, there can be mentioned a resinmixture comprising an acrylic resin and an epoxy resin, the resinmixture described above with addition of a filler, melamine, acryl,polystyrol and polyimide, as well as polyurethane and silicone;although, it is necessary that they have a property of withstanding thesoldering temperature and have a resistance to the exposure of a fluxand a cleaning solvent.

Advantageous effects obtained by typical examples among those disclosed,although not limited thereto, in accordance with the present inventionare briefly explained below.

(1) Since the elastic structural material is disposed on the flatsurface on the rear face of the substrate base material by adopting asurface wiring structure in which the elastic structural material isdisposed on the rear face of the substrate base material of the wiringsubstrate, and the insulation film is formed on the main surface of thewirings formed on the main surface of the substrate base material, theelastic structural material can be mounted with a higher accuracy andstably to the substrate base material in a voidless manner and, sincethe size and the shape of the elastic structural material are madestable, the bonding step for the semiconductor chip is also stable,thereby enabling assembling at a higher yield.

(2) Since the signal wiring layer and the power source ground wiringlayer can be separated into different layers by making the wirings ofthe wiring substrate into a multi-wiring layer structure, an excellentelectric characteristic in view of noise resistance can be attained.

(3) Since external terminals of the semiconductor chip can be disposedat the central portion or the peripheral portion, and the bumpelectrodes connected to the external terminals can be disposed to theinside, outside or both of the regions outward of the outercircumference of the semiconductor chip, the invention is applicable topackage structures of various types and variations.

(4) Since the edge position of the substrate base material can beoptimized relative to the elastic structural material by setting thedistance between the end of the elastic structural material of thesemiconductor chip on the side of the external terminals and the end ofthe substrate base material of the wirings substrate based on theingredients of the elastic structural material, a variation in theheight of the bump electrodes is not caused, thereby avoiding anydifficulty in filling the sealant caused by an enlarged sealing regionfor the opening of the elastic structural material and it is possible toprevent contamination of wirings caused by the bleeding of ingredientsor evaporative ingredients of the elastic structural material.

(5) Since the outer size of the package can be optimized by setting therelation for the distance M2 between the end of the substrate basematerial of the wiring substrate and the end of the elastic structuralmaterial and for the distance M1 between the end of the semiconductorchip and the end of the substrate base material at the outercircumference of the semiconductor integrated circuit device within arange: M1>M2>0, the outermost circumference of the package is not formedby the semiconductor chip, so that a possibility of inducing chip cracksis reduced during the assembling step, as well as during withdrawal andinsertion of receptacles and tray transportation, and the circuitsurface of the semiconductor chip is not exposed to the outside, therebymaking it possible to improve the reliability. Further, since theperipheral protrusions of the elastic structural material after printingdo not interfere with the bonding portion of the semiconductor chip, itis possible to prevent bonding failure upon appending the chip,worsening of the flatness of the wiring substrate and lowering of thereliability.

(6) Since the planar S-shaped wiring can be obtained by forming thewiring of the wiring substrate such that the fixed portion with thesubstrate base material and top end portion connected to the externalterminal of the semiconductor chip are displaced at least by more thanthe width of the wiring, a stable and suitable S-shaped lead can beformed because a sag due to the original planar S-shaped configurationcan be obtained by a simple driving down movement of a typical wirebonder, so that a stable S-shaped configuration can be formed for thelead with no requirement of a soft-modified special wire bonder, andfurther, the contact time upon bonding can also be shortened since thebonding tool trace can also be simplified.

(7) Since the beam wiring can be attained by forming the wiring of thewiring substrate as a cantilever structure which is fixed at one end tothe substrate base material, it is possible to overcome such problems asoccur in notched wirings wherein cutting is often impossible duringbonding due to the variation of the size of the notches and, even if thewiring can be cut, it may be cut at a portion different from the desirednotch, or it may be cut before the plating step for the wiring substratebecause of the excessively narrowed portion, thereby failing to depositplating.

(8) Since the end of the opening of the surface protection film on thesemiconductor chip is set to a size within a range wherein the wiringdoes not interfere with the surface protection film when the bondingtool is driven down, it is possible to overcome the problem that thesurface protection film or the semiconductor chip suffers from damages(on the semiconductor chip) by the driving down pressure of the tool,and the ingredients of the surface protection film are prevented frombeing deposited on the bonding portion at the lower surface of the leadto cause contamination and to worsen the bondability.

(9) Since the effective area of the wired portion can be enlarged byconnecting the wiring on the notch terminal end of the wiring substrateto an opposing land portion of the wiring, longitudinally or laterallyextending the wiring in the vacant regions of the wirings or connectingthe adjacent wirings to each other, it is possible to increase thebonding strength between the wiring and the substrate base material andobtain a stable notch cutting performance.

(10) Since a wide elastic material structure can be attained by formingthe elastic structural material in a larger range over the entirecircumference at least by more than the width of the protrusions on theouter circumference formed in the elastic structural material ascompared with the outer size of the semiconductor chip, protrusions onthe periphery of the elastic structural member are located outside ofthe semiconductor chip after the appending of the semiconductor chip,and it can be bonded substantially on the flat portion of the elasticstructural material, whereby the warping of the wiring substrate issuppressed. Further, since a large coating area of adhesive can beprovided, a not bonded portion caused by insufficient adhesive is lesslikely to occur, and the adhesive tends to extrude out uniformly aroundthe periphery of the semiconductor chip, so that a package of excellentmoisture proofness and reliability can be constituted with out applyingan additional peripheral sealing.

(11) In a case of forming the elastic structural material as dividedportions which are spaced so as to be not bonded on the externalterminals of the semiconductor chip, when each end of the spaces atwhich the divided elastic structural materials are opposed is formed asa grooved shape, the metal mask bridge portion can be restricted tonarrow the groove of the elastic structural material in thegroove-fillage technique of the elastic structural material, so that thegroove-fillage of the elastic structural material can be improved.

(12) If a plurality of grooves are formed at each of the ends of theelastic structural material, the strength of the groove-forming metalmask can be improved.

(13) When a stopping dam for sealant flow is previously formed at thegrooves at each of the ends of the spaces at which the dividedstructural materials are opposed, the groove-fillage in the sealing stepcan further be improved.

(14) By pre-forming stud bumps on the external terminals of thesemiconductor chip and connecting the external terminals of thesemiconductor chip and the wirings of the wiring substrate by way of thestud bumps, problems in the bondability and the possibility of damagecan be solved in the inner lead bonding technique, whereby thebondability is improved by the stud bumps and, further, the possibilityof damage can be prevented.

(15) By supplying the solder so as to previously surround the wirings ofthe wiring substrate and connecting the external terminals of thesemiconductor chip and the external terminals of the wiring substrate byway of the solder, bondability can be improved and damage can besuppressed in the bonding technique.

(16) By using the stud bumps, for example, made of solder or Au so as tosurround the wirings of the wiring substrate, and by connecting thewirings of the wiring substrate and the external terminals of thesemiconductor chip by way of the stud bumps, the bondability can beimproved and the possibility of damage can be suppressed in the bondingtechnique.

(17) By connecting the wirings of the wiring substrate and the externalterminals of the semiconductor chip by using an Al, solder or Au wire,the problem, for example, of bondability or damage can be solved, and itis possible to attain connection by the concept of a typical wirebonding, not by the inner lead bonding, such as a TAB.

(18) By forming the lateral size of the wiring of the wiring substratesuch that the size is gradually narrowed from the end of the substratebase material of the wiring substrate to the top end of the wiring andthe lateral size is made constant from a predetermined position, andsetting the size and the shape of the wiring such that the bendingstress ratio α is from 1.2 to 1.5, since a suitable S-shapedconfiguration can be formed by merely driving down the bonding toolvertically with no return of the bonding tool, a lead of a stably shapedconfiguration can be formed without requiring a special soft-modifiedwire bonder; and, further, the contact time upon bonding can also beshortened since the trace of the bonding tool can be simplified.

(19) By using the electroconductive material as a core material for thewiring structure of the wiring substrate and applying only Au plating tothe surface, since both the hardness and the brittleness of the lead arelowered as compared with a case of applying Ni-plating between the corematerial of the conductive material, such as Cu, and Au plating, cracksare less likely in the lead itself, and damage to the semiconductor chipat the counter bonding face can also be moderated.

(20) By forming the wirings on the rear face of the substrate basematerial of the wiring substrate, forming the insulation film on therear face of the wirings and disposing the elastic structure material onthe rear face of the insulation film, since a rear face wiringinsulation film structure can be obtained, direct contact of the elasticstructural material with the wiring can be prevented and contact of theelastic structural material to the roughened surface of the substratebase material can also be prevented, so that bleeding of the lowmolecular weight ingredients of the elastic structure material can besuppressed and, further, the uneven wiring surface can be flattened bycoating the insulation film making it possible to avoid disadvantages,such as the creation of voids upon forming the elastic structuralmaterial.

(21) In the surface wiring structure, since the opening of theinsulation film is formed by defining the coating range of theinsulation film material, the fabrication accuracy for the hole diametercan further be improved as compared with a case of forming the openingby machining the substrate base material of the wiring substrate of therear face wiring structure.

(22) By setting the thickness of the insulation film by determining thecoating condition for the insulation film material in the surface wiringstructure, since the film can be coated stably at a further reducedthickness and the bump land disposed at a higher density with a smalldiameter can be formed as compared with the substrate base material, asmaller bump electrode can be joined more satisfactorily.

(23) In the surface wiring structure, since the pitch for thearrangement of the bump electrodes can be reduced as compared with therear face wiring structure, it is possible to constitute a semiconductorpackage having output terminals at higher density.

(24) As the substrate body and substrate protruding parts of the thinfilm wiring substrate in the semiconductor device (CSP) are formed in aone-piece construction, the substrate protruding-parts are not formedindependently and, therefore, do not have to be formed of costlymaterials. This lowers the cost of manufacturing the semiconductordevice.

(25) By providing the substrate protruding parts outside the openings inthe thin film wiring substrate, when a sealing resin is applied via theopenings, the sealing parts are formed as a bridge between the substrateprotruding parts and the semiconductor chip. In this way, a stable sealcan be obtained, sealing properties are improved, and consequentlyhumidity resistance is improved.

(26) When the bump electrodes are formed, even if the semiconductordevice is subjected to reflow after it absorbs moisture, water vaporproduced during reflow can be released to the outside via the elasticstructure as the side faces in a predetermined direction of the elasticstructure are exposed to the outside, and reflow tolerance is therebyimproved.

(27) By forming the elastic structure of a porous fluoride resin, thewater vapor produced during reflow can be released to the outside and atthe same time, penetration of moisture into the semiconductor device isprevented by the water repelling properties of the fluoride resin. As aresult, deterioration of the electrical characteristics of thesemiconductor device is reduced.

(28) By incorporating a coloring agent in the elastic structure,transmittance of light in the elastic structure can be reduced withoutaffecting the basic physical properties of the elastic structure. Inthis way, the circuit of the semiconductor chip can be shielded fromlight, ultraviolet light which would cause incorrect operation of thesemiconductor chip is blocked, and operational stability of theelectrical circuit of the semiconductor device is improved.

(29) In the thin film wiring substrate, by making the connectionsbetween the wiring and bump lands wide, concentration of stress in theconnections is prevented. Hence, even if the wiring deforms due tothermal contraction and expansion together with the tape base materialduring temperature cycles, rupture of leads is prevented in theconnecting parts 4 s between the wiring and bump lands.

(30) By forming the exposed parts in the elastic structure, even whenthe internal pressure of the elastic structure rises as during reflowfor example, gas can be released to the outside from the exposed partsof the elastic structure. In this way, occurrence of the popcornphenomenon which damages the sealing parts, etc., is prevented, and as aresult the reliability of the semiconductor device is improved.

This concludes the description of the example embodiments. Although thepresent invention has been described with reference to a number ofillustrative embodiments thereof, it should be understood that numerousother modifications and embodiments can be devised by those skilled inthe art that will fall within the spirit and scope of the principles ofthis invention. More particularly, reasonable variations andmodifications are possible in the component parts and/or arrangements ofthe subject combination arrangement within the scope of the foregoingdisclosure, the drawings and the appended claims without departing fromthe spirit of the invention. In addition to variations and modificationsin the component parts and/or arrangements, alternative uses will alsobe apparent to those skilled in the art.

1. A semiconductor device comprising: a semiconductor chip having aplurality of semiconductor elements and a plurality of externalterminals formed in a main surface thereof; an elastic layer provided onthe main surface of the semiconductor chip in a manner to expose theplurality of external terminals; an insulating tape provided on theelastic layer and having an opening to expose the plurality of externalterminals, the opening being defined by an edge of the insulating tape;a plurality of leads provided on a surface of the insulating tape,wherein each of the plurality of leads has a first portion disposed onthe insulating tape and a second portion which extends across the edgeof the insulating tape and is in the opening of the insulating tape,each of the second portions being electrically connected with acorresponding one of the external terminals; and a plurality of bumpelectrodes formed on the first portions of the plurality of leads andbeing electrically connected to the plurality of leads, respectively,wherein each of the plurality of leads includes a copper lead as corematerial thereof, wherein the copper lead of each of the plurality ofleads has gold-plating applied on its surfaces and wherein a length ofthe second portion of each of the plurality of leads is longer than astraight line distance from the edge of the insulating tape to thecorresponding one of the external terminals.
 2. A semiconductor deviceaccording to claim 1, wherein no other metallic material exists betweenthe copper lead and the gold-plating.
 3. A semiconductor deviceaccording to claim 1, wherein the plurality of leads are disposedbetween the elastic layer and the insulating tape, and wherein theplurality of bump electrodes are contacting the corresponding ones ofthe plurality of leads via through holes formed in the insulating tape,respectively.
 4. A semiconductor device according to claim 1, whereineach of the plurality of leads is disposed to form a substantiallystraight line pattern in a plane view and to form a bended pattern in asectional view.
 5. A semiconductor device according to claim 1, whereinthe plurality of leads are disposed between the elastic layer and theinsulating tape.
 6. A semiconductor device according to claim 5, whereineach of the plurality of leads is disposed to form a substantiallystraight line pattern in a plane view and to form a bended pattern in asectional view.
 7. A semiconductor device according to claim 6, whereinthe plurality of bump electrodes are contacting the corresponding onesof the plurality of leads via through holes formed in the insulatingtape, respectively.
 8. A semiconductor device according to claim 7,wherein no other metallic material exists between the copper lead andthe gold-plating.
 9. A semiconductor device according to claim 5,wherein no other metallic material exists between the copper lead andthe gold-plating. 10-33. (canceled)